From 6bde0bb72a4f54431bcfea743f69edada4c513c1 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Wed, 1 Jul 2020 01:40:30 +0100 Subject: Fix to comments --- data/accumulator.htl | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 data/accumulator.htl (limited to 'data/accumulator.htl') diff --git a/data/accumulator.htl b/data/accumulator.htl new file mode 100644 index 0000000..99e3ccb --- /dev/null +++ b/data/accumulator.htl @@ -0,0 +1,41 @@ +main() { + datapath { + 16: reg_9 <= 32'd1; + 15: reg_13[32'd0] <= reg_9; + 14: reg_8 <= 32'd2; + 13: reg_13[32'd1] <= reg_8; + 12: reg_7 <= 32'd3; + 11: reg_13[32'd2] <= reg_7; + 10: reg_3 <= 32'd0; + 9: ; + 8: reg_1 <= 32'd0; + 7: reg_6 <= 32'd0; + 6: reg_5 <= reg_13[{{{reg_6 + 32'd0} + + {reg_1 * 32'd4}} / 32'd4}]; + 5: reg_3 <= {reg_3 + {reg_5 + 32'd0}}; + 4: reg_1 <= {reg_1 + 32'd1}; + 3: ; + 2: reg_4 <= reg_3; + 1: reg_11 <= 1'd1; reg_12 <= reg_4; + } + + controllogic { + 16: reg_10 <= 32'd15; + 15: reg_10 <= 32'd14; + 14: reg_10 <= 32'd13; + 13: reg_10 <= 32'd12; + 12: reg_10 <= 32'd11; + 11: reg_10 <= 32'd10; + 10: reg_10 <= 32'd9; + 9: reg_10 <= 32'd8; + 8: reg_10 <= 32'd7; + 7: reg_10 <= 32'd6; + 6: reg_10 <= 32'd5; + 5: reg_10 <= 32'd4; + 4: reg_10 <= 32'd3; + 3: reg_10 <= ({$signed(reg_1) < $signed(32'd3)} + ? 32'd7 : 32'd2); + 2: reg_10 <= 32'd1; + 1: ; + } +} -- cgit