From 36dc41477a21e15b81b09985c9505ea1b5f10817 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Mon, 2 Nov 2020 00:27:18 +0000
Subject: Add some more content

---
 data/accumulator.v | 192 +++++++++++++++++++++++++++++++++++++++--------------
 1 file changed, 142 insertions(+), 50 deletions(-)

(limited to 'data/accumulator.v')

diff --git a/data/accumulator.v b/data/accumulator.v
index 146176d..799756f 100644
--- a/data/accumulator.v
+++ b/data/accumulator.v
@@ -1,53 +1,145 @@
-module main(reset, clk, finish, return_val);
-  reg [31:0] stack [2:0];
-  input [0:0] clk, reset;
-  output reg [31:0] return_val;
-  output reg [0:0] finish;
-  reg [31:0] reg_8, reg_4, state, reg_6,
-             reg_1, reg_9, reg_5, reg_3, reg_7;
-  always @(posedge clk)
-    case (state)
-      32'd16: reg_9 <= 32'd1;
-      32'd15: stack[32'd0] <= reg_9;
-      32'd14: reg_8 <= 32'd2;
-      32'd13: stack[32'd1] <= reg_8;
-      32'd12: reg_7 <= 32'd3;
-      32'd11: stack[32'd2] <= reg_7;
-      32'd10: reg_3 <= 32'd0;
-      32'd9: ;
-      32'd8: reg_1 <= 32'd0;
-      32'd7: reg_6 <= 32'd0;
-      32'd6: reg_5 <= stack[{{{reg_6 + 32'd0}
-                           + {reg_1 * 32'd4}} / 32'd4}];
-      32'd5: reg_3 <= {reg_3 + {reg_5 + 32'd0}};
-      32'd4: reg_1 <= {reg_1 + 32'd1};
-      32'd3: ;
-      32'd2: reg_4 <= reg_3;
-      32'd1: begin finish = 1'd1; return_val = reg_4; end
-      default:;
-    endcase
-  always @(posedge clk)
-    if ({reset == 1'd1})
-      state <= 32'd16;
-    else
-      case (state)
-        32'd16: state <= 32'd15;
-        32'd15: state <= 32'd14;
-        32'd14: state <= 32'd13;
-        32'd13: state <= 32'd12;
-        32'd12: state <= 32'd11;
-        32'd11: state <= 32'd10;
-        32'd10: state <= 32'd9;
-        32'd9: state <= 32'd8;
-        32'd8: state <= 32'd7;
-        32'd7: state <= 32'd6;
-        32'd6: state <= 32'd5;
-        32'd5: state <= 32'd4;
-        32'd4: state <= 32'd3;
-        32'd3: state <= ({$signed(reg_1) < $signed(32'd3)}
-                               ? 32'd7 : 32'd2);
-        32'd2: state <= 32'd1;
-        32'd1: ;
+module main(reg_13, reg_14, reg_15, reg_10, reg_11);
+  always @(posedge reg_15)
+    if ({reg_14 == 32'd1}) begin
+      reg_9 <= 32'd15;
+    end else begin
+      case (reg_9)
+        32'd8: begin
+          reg_9 <= 32'd7;
+        end
+        32'd4: begin
+          reg_9 <= 32'd3;
+        end
+        32'd12: begin
+          reg_9 <= 32'd11;
+        end
+        32'd2: begin
+          reg_9 <= 32'd1;
+        end
+        32'd10: begin
+          reg_9 <= 32'd9;
+        end
+        32'd6: begin
+          reg_9 <= 32'd5;
+        end
+        32'd14: begin
+          reg_9 <= 32'd13;
+        end
+        32'd1: begin
+          ;
+        end
+        32'd9: begin
+          reg_9 <= 32'd8;
+        end
+        32'd5: begin
+          reg_9 <= 32'd4;
+        end
+        32'd13: begin
+          reg_9 <= 32'd12;
+        end
+        32'd3: begin
+          reg_9 <= ({$signed(reg_1) < $signed(32'd3)} ? 32'd7 : 32'd2);
+        end
+        32'd11: begin
+          reg_9 <= 32'd10;
+        end
+        32'd7: begin
+          reg_9 <= 32'd6;
+        end
+        32'd15: begin
+          reg_9 <= 32'd14;
+        end
         default:;
       endcase
+    end
+  always @(posedge reg_15)
+    case (reg_9)
+      32'd8: begin
+        reg_1 <= 32'd0;
+      end
+      32'd4: begin
+        reg_1 <= {reg_1 + 32'd1};
+      end
+      32'd12: begin
+        reg_12[32'd1] <= reg_7;
+      end
+      32'd2: begin
+        reg_3 <= reg_2;
+      end
+      32'd10: begin
+        reg_12[32'd2] <= reg_6;
+      end
+      32'd6: begin
+        reg_4 <= reg_12[{{{reg_5 + 32'd0} + {reg_1 * 32'd4}} / 32'd4}];
+      end
+      32'd14: begin
+        reg_12[32'd0] <= reg_8;
+      end
+      32'd1: begin
+        reg_10 = 32'd1;
+        reg_11 = reg_3;
+      end
+      32'd9: begin
+        reg_2 <= 32'd0;
+      end
+      32'd5: begin
+        reg_2 <= {{reg_2 + reg_4} + 32'd0};
+      end
+      32'd13: begin
+        reg_7 <= 32'd2;
+      end
+      32'd3: begin
+        ;
+      end
+      32'd11: begin
+        reg_6 <= 32'd3;
+      end
+      32'd7: begin
+        reg_5 <= 32'd0;
+      end
+      32'd15: begin
+        reg_8 <= 32'd1;
+      end
+      default:;
+    endcase
+  reg [31:0] reg_12 [2:0];
+  reg [31:0] reg_8;
+  reg [31:0] reg_4;
+  reg [31:0] reg_2;
+  output reg [0:0] reg_10;
+  reg [31:0] reg_6;
+  input [0:0] reg_14;
+  reg [31:0] reg_1;
+  reg [31:0] reg_9;
+  reg [31:0] reg_5;
+  input [0:0] reg_13;
+  reg [31:0] reg_3;
+  output reg [31:0] reg_11;
+  reg [31:0] reg_7;
+  input [0:0] reg_15;
+endmodule
+
+module testbench;
+   reg start, reset, clk;
+   wire finish;
+   wire [31:0] return_val;
+
+   main m(start, reset, clk, finish, return_val);
+
+   initial begin
+      clk = 0;
+      start = 0;
+      reset = 0;
+      @(posedge clk) reset = 1;
+      @(posedge clk) reset = 0;
+   end
+
+   always #5 clk = ~clk;
+
+   always @(posedge clk) begin
+      if (finish == 1) begin
+         $display("finished: %d", return_val);
+         $finish;
+      end
+   end
 endmodule
-- 
cgit