From 6bde0bb72a4f54431bcfea743f69edada4c513c1 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 1 Jul 2020 01:40:30 +0100
Subject: Fix to comments

---
 data/accumulator.c   |  7 +++++++
 data/accumulator.htl | 41 ++++++++++++++++++++++++++++++++++++++++
 data/accumulator.rtl | 18 ++++++++++++++++++
 data/accumulator.v   | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 119 insertions(+)
 create mode 100644 data/accumulator.c
 create mode 100644 data/accumulator.htl
 create mode 100644 data/accumulator.rtl
 create mode 100644 data/accumulator.v

(limited to 'data')

diff --git a/data/accumulator.c b/data/accumulator.c
new file mode 100644
index 0000000..7d78a61
--- /dev/null
+++ b/data/accumulator.c
@@ -0,0 +1,7 @@
+int main() {
+    int x[3] = {1, 2, 3};
+    int sum = 0, incr = 1;
+    for (int i = 0; i < 3; i=i+incr)
+        sum += x[i];
+    return sum;
+}
diff --git a/data/accumulator.htl b/data/accumulator.htl
new file mode 100644
index 0000000..99e3ccb
--- /dev/null
+++ b/data/accumulator.htl
@@ -0,0 +1,41 @@
+main() {
+  datapath {
+   16:	reg_9 <= 32'd1;
+   15:	reg_13[32'd0] <= reg_9;
+   14:	reg_8 <= 32'd2;
+   13:	reg_13[32'd1] <= reg_8;
+   12:	reg_7 <= 32'd3;
+   11:	reg_13[32'd2] <= reg_7;
+   10:	reg_3 <= 32'd0;
+    9:	;
+    8:	reg_1 <= 32'd0;
+    7:	reg_6 <= 32'd0;
+    6:	reg_5 <= reg_13[{{{reg_6 + 32'd0}
+                        + {reg_1 * 32'd4}} / 32'd4}];
+    5:	reg_3 <= {reg_3 + {reg_5 + 32'd0}};
+    4:	reg_1 <= {reg_1 + 32'd1};
+    3:	;
+    2:	reg_4 <= reg_3;
+    1:	reg_11 <= 1'd1; reg_12 <= reg_4;
+  }
+
+  controllogic {
+   16:	reg_10 <= 32'd15;
+   15:	reg_10 <= 32'd14;
+   14:	reg_10 <= 32'd13;
+   13:	reg_10 <= 32'd12;
+   12:	reg_10 <= 32'd11;
+   11:	reg_10 <= 32'd10;
+   10:	reg_10 <= 32'd9;
+    9:	reg_10 <= 32'd8;
+    8:	reg_10 <= 32'd7;
+    7:	reg_10 <= 32'd6;
+    6:	reg_10 <= 32'd5;
+    5:	reg_10 <= 32'd4;
+    4:	reg_10 <= 32'd3;
+    3:	reg_10 <= ({$signed(reg_1) < $signed(32'd3)}
+                        ? 32'd7 : 32'd2);
+    2:	reg_10 <= 32'd1;
+    1:	;
+  }
+}
diff --git a/data/accumulator.rtl b/data/accumulator.rtl
new file mode 100644
index 0000000..a6b528c
--- /dev/null
+++ b/data/accumulator.rtl
@@ -0,0 +1,18 @@
+main() {
+   16:	x9 = 1
+   15:	int32[stack(0)] = x9
+   14:	x8 = 2
+   13:	int32[stack(4)] = x8
+   12:	x7 = 3
+   11:	int32[stack(8)] = x7
+   10:	x3 = 0
+    9:	nop
+    8:	x1 = 0
+    7:	x6 = stack(0) (int)
+    6:	x5 = int32[x6 + x1 * 4 + 0]
+    5:	x3 = x3 + x5 + 0 (int)
+    4:	x1 = x1 + 1 (int)
+    3:	if (x1 <s 3) goto 7 else goto 2
+    2:	x4 = x3
+    1:	return x4
+}
diff --git a/data/accumulator.v b/data/accumulator.v
new file mode 100644
index 0000000..baabfe3
--- /dev/null
+++ b/data/accumulator.v
@@ -0,0 +1,53 @@
+module main(reg_14, reg_15, reg_16, reg_11, reg_12);
+  always @(posedge reg_16)
+    if ({reg_15 == 1'd1})
+      reg_10 <= 32'd16;
+    else
+      case (reg_10)
+        32'd16: reg_10 <= 32'd15;
+        32'd8: reg_10 <= 32'd7;
+        32'd4: reg_10 <= 32'd3;
+        32'd12: reg_10 <= 32'd11;
+        32'd2: reg_10 <= 32'd1;
+        32'd10: reg_10 <= 32'd9;
+        32'd6: reg_10 <= 32'd5;
+        32'd14: reg_10 <= 32'd13;
+        32'd1: ;
+        32'd9: reg_10 <= 32'd8;
+        32'd5: reg_10 <= 32'd4;
+        32'd13: reg_10 <= 32'd12;
+        32'd3: reg_10 <= ({$signed(reg_1) < $signed(32'd3)}
+                               ? 32'd7 : 32'd2);
+        32'd11: reg_10 <= 32'd10;
+        32'd7: reg_10 <= 32'd6;
+        32'd15: reg_10 <= 32'd14;
+        default:;
+      endcase
+  always @(posedge reg_16)
+    case (reg_10)
+      32'd16: reg_9 <= 32'd1;
+      32'd8: reg_1 <= 32'd0;
+      32'd4: reg_1 <= {reg_1 + 32'd1};
+      32'd12: reg_7 <= 32'd3;
+      32'd2: reg_4 <= reg_3;
+      32'd10: reg_3 <= 32'd0;
+      32'd6: reg_5 <= reg_13[{{{reg_6 + 32'd0}
+                             + {reg_1 * 32'd4}} / 32'd4}];
+      32'd14: reg_8 <= 32'd2;
+      32'd1: begin reg_11 = 1'd1; reg_12 = reg_4; end
+      32'd9: ;
+      32'd5: reg_3 <= {reg_3 + {reg_5 + 32'd0}};
+      32'd13: reg_13[32'd1] <= reg_8;
+      32'd3: ;
+      32'd11: reg_13[32'd2] <= reg_7;
+      32'd7: reg_6 <= 32'd0;
+      32'd15: reg_13[32'd0] <= reg_9;
+      default:;
+    endcase
+  reg [31:0] reg_13 [2:0];
+  input [0:0] reg_16, reg_14, reg_15;
+  reg [31:0] reg_8, reg_4, reg_10, reg_6,
+             reg_1, reg_9, reg_5, reg_3, reg_7;
+  output reg [31:0] reg_12;
+  output reg [0:0] reg_11;
+endmodule
-- 
cgit