From fb42c6f69b1f3e5d5362fcb483dc195201a63fbd Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 14 Apr 2021 11:53:23 +0100
Subject: Fix main diagram

---
 data/accumulator.c   |   5 +-
 data/accumulator.htl |  24 +++++---
 data/accumulator.v   | 108 +++++++++++++++++++++--------------
 data/accumulator2.v  | 156 +++++++++++++++++++++++++++++++++++++++++++--------
 4 files changed, 218 insertions(+), 75 deletions(-)

(limited to 'data')

diff --git a/data/accumulator.c b/data/accumulator.c
index f8b5e32..217851c 100644
--- a/data/accumulator.c
+++ b/data/accumulator.c
@@ -1,4 +1,5 @@
 int main() {
-    int x[1] = {3};
-    return x[0];
+    int x[2] = {3, 6};
+    int i = 1;
+    return x[i];
 }
diff --git a/data/accumulator.htl b/data/accumulator.htl
index ecab36f..6f7ec5f 100644
--- a/data/accumulator.htl
+++ b/data/accumulator.htl
@@ -1,16 +1,24 @@
 main() {
   datapath {
-    4:	reg_2 <= 32'd3;
-    3:	reg_6[32'd0] <= reg_2;
-    2:	reg_1 <= reg_6[32'd0];
-    1:	reg_4 = 32'd1;
-reg_5 = reg_1;
+    8:	reg_5 <= 32'd3;
+    7:	reg_9[32'd0] <= reg_5;
+    6:	reg_4 <= 32'd6;
+    5:	reg_9[32'd1] <= reg_4;
+    4:	reg_1 <= 32'd1;
+    3:	reg_3 <= 32'd0;
+    2:	reg_2 <= reg_9[{{{reg_3 + 32'd0} + {reg_1 * 32'd4}} / 32'd4}];
+    1:	reg_7 = 32'd1;
+reg_8 = reg_2;
   }
 
   controllogic {
-    4:	reg_3 <= 32'd3;
-    3:	reg_3 <= 32'd2;
-    2:	reg_3 <= 32'd1;
+    8:	reg_6 <= 32'd7;
+    7:	reg_6 <= 32'd6;
+    6:	reg_6 <= 32'd5;
+    5:	reg_6 <= 32'd4;
+    4:	reg_6 <= 32'd3;
+    3:	reg_6 <= 32'd2;
+    2:	reg_6 <= 32'd1;
     1:	;
   }
 }
diff --git a/data/accumulator.v b/data/accumulator.v
index aaed3da..f0057b5 100644
--- a/data/accumulator.v
+++ b/data/accumulator.v
@@ -1,46 +1,68 @@
+
 module main(reset, clk, finish, return_val);
-  input [0:0] clk, reset;
-  output reg [31:0] return_val = 0;
-  output reg [0:0] finish = 0;
-  reg [0:0] en = 0, wr_en = 0, u_en = 0;
-  reg [31:0] state = 0, d_out = 0, d_in = 0;
-  reg [31:0] reg_1 = 0, addr = 0, reg_2 = 0;
-  reg [31:0] stack [0:0];
-  always @(negedge clk)
-    if ({u_en != en}) begin
-      if (wr_en) stack[addr] <= d_in;
-      else d_out <= stack[addr];
-      en <= u_en;
-    end
-  always @(posedge clk)
-    case (state)
-      32'd6: reg_1 <= d_out;
-      32'd4: reg_2 <= 32'd3;
-      32'd3: begin
-        u_en <= ( ! u_en);
-        wr_en <= 32'd1;
-        d_in <= reg_2;
-        addr <= 32'd0;
+input [0:0] reset, clk;
+output reg [0:0] finish = 0;
+output reg [31:0] return_val = 0;
+reg [31:0] reg_3 = 0, addr = 0, d_in = 0, reg_5 = 0, wr_en = 0;
+reg [0:0] en = 0, u_en = 0;
+reg [31:0] state = 0, reg_2 = 0, reg_4 = 0, d_out = 0, reg_1 = 0;
+reg [31:0] stack [1:0];
+always @(negedge clk)
+if ({u_en != en}) begin
+if (wr_en) stack[addr] <= d_in; else d_out <= stack[addr];
+en <= u_en;
+end
+always @(posedge clk)
+case (state)
+32'd11: reg_2 <= d_out;
+32'd8: reg_5 <= 32'd3;
+32'd7: begin u_en <= ( ! u_en); wr_en <= 32'd1;
+d_in <= reg_5; addr <= 32'd0; end
+32'd6: reg_4 <= 32'd6;
+32'd5: begin u_en <= ( ! u_en); wr_en <= 32'd1;
+d_in <= reg_4; addr <= 32'd1; end
+32'd4: reg_1 <= 32'd1;
+32'd3: reg_3 <= 32'd0;
+32'd2: begin u_en <= ( ! u_en); wr_en <= 32'd0;
+addr <= {{{reg_3 + 32'd0} + {reg_1 * 32'd4}} / 32'd4}; end
+32'd1: begin finish = 32'd1; return_val = reg_2; end
+default: ;
+endcase
+always @(posedge clk)
+if ({reset == 32'd1}) state <= 32'd8;
+else case (state)
+32'd11: state <= 32'd1;
+32'd4: state <= 32'd3;
+32'd8: state <= 32'd7;
+32'd3: state <= 32'd2;
+32'd7: state <= 32'd6;
+32'd2: state <= 32'd11;
+
+module testbench;
+   reg start, reset, clk;
+   wire finish;
+   wire [31:0] return_val;
+   reg [31:0] cycles;
+
+   main m(reset, clk, finish, return_val);
+
+   initial begin
+      clk = 0;
+      start = 0;
+      reset = 0;
+      @(posedge clk) reset = 1;
+      @(posedge clk) reset = 0;
+      cycles = 0;
+   end
+
+   always #5 clk = ~clk;
+
+   always @(posedge clk) begin
+      if (finish == 1) begin
+         $display("cycles: %0d", cycles);
+         $display("finished: %0d", return_val);
+         $finish;
       end
-      32'd2: begin
-        u_en <= ( ! u_en);
-        wr_en <= 32'd0;
-        addr <= 32'd0;
-      end
-      32'd1: begin
-        finish = 32'd1;
-        return_val = reg_1;
-      end
-      default:;
-    endcase
-  always @(posedge clk)
-    if ({reset == 32'd1}) state <= 32'd4;
-    else case (state)
-        32'd6: state <= 32'd1;
-        32'd4: state <= 32'd3;
-        32'd3: state <= 32'd2;
-        32'd2: state <= 32'd6;
-        32'd1: ;
-        default:;
-    endcase
+      cycles <= cycles + 1;
+   end
 endmodule
diff --git a/data/accumulator2.v b/data/accumulator2.v
index c7bcc59..bb4c198 100644
--- a/data/accumulator2.v
+++ b/data/accumulator2.v
@@ -1,26 +1,138 @@
-always @(posedge clk)
-    if ({reset == 1'd1})
-      state <= 32'd16;
-    else
+module main(start, reset, clk, finish, return_val);
+  reg [31:0] reg_15 = 0;
+  output reg [0:0] finish = 0;
+  input [0:0] reset;
+  reg [31:0] reg_3 = 0;
+  reg [31:0] reg_13 = 0;
+  reg [31:0] reg_5 = 0;
+  reg [0:0] reg_17 = 0;
+  reg [31:0] reg_1 = 0;
+  reg [0:0] reg_14 = 0;
+  reg [31:0] state = 0;
+  input [0:0] start;
+  reg [0:0] reg_18 = 0;
+  reg [31:0] reg_2 = 0;
+  input [0:0] clk;
+  reg [31:0] reg_4 = 0;
+  output reg [31:0] return_val = 0;
+  reg [31:0] reg_16 = 0;
+  reg [31:0] stack [1:0];
+  always @(negedge clk) begin
+    if ({reg_18 != reg_14}) begin
+      if (reg_17) begin
+        stack[reg_13] <= reg_15;
+      end else begin
+        reg_16 <= stack[reg_13];
+      end
+      reg_14 <= reg_18;
+    end else begin
+      ;
+    end
+  end
+  always @(posedge clk) begin
+    case (state)
+      32'd11: begin
+        reg_2 <= reg_16;
+      end
+      32'd8: begin
+        reg_5 <= 32'd3;
+      end
+      32'd7: begin
+        reg_18 <= ( ! reg_18);
+        reg_17 <= 32'd1;
+        reg_15 <= reg_5;
+        reg_13 <= 32'd0;
+      end
+      32'd6: begin
+        reg_4 <= 32'd6;
+      end
+      32'd5: begin
+        reg_18 <= ( ! reg_18);
+        reg_17 <= 32'd1;
+        reg_15 <= reg_4;
+        reg_13 <= 32'd1;
+      end
+      32'd4: begin
+        reg_1 <= 32'd1;
+      end
+      32'd3: begin
+        reg_3 <= 32'd0;
+      end
+      32'd2: begin
+        reg_18 <= ( ! reg_18);
+        reg_17 <= 32'd0;
+        reg_13 <= {{{reg_3 + 32'd0} + {reg_1 * 32'd4}} / 32'd4};
+      end
+      32'd1: begin
+        finish = 32'd1;
+        return_val = reg_2;
+      end
+      default:;
+    endcase
+  end
+  always @(posedge clk) begin
+    if ({reset == 32'd1}) begin
+      state <= 32'd8;
+    end else begin
       case (state)
-        32'd16: state <= 32'd15;
-        32'd15: state <= 32'd14;
-        32'd14: state <= 32'd13;
-        32'd13: state <= 32'd12;
-        32'd12: state <= 32'd11;
-        32'd11: state <= 32'd10;
-        32'd10: state <= 32'd9;
-        32'd9: state <= 32'd8;
-        32'd8: state <= 32'd7;
-        32'd7: state <= 32'd6;
-        32'd6: state <= 32'd5;
-        32'd5: state <= 32'd4;
-        32'd4: state <= 32'd3;
-        32'd3: state <=
-          ({$signed(reg_1) < $signed(32'd3)}
-             ? 32'd7 : 32'd2);
-        32'd2: state <= 32'd1;
-        32'd1: ;
+        32'd11: begin
+          state <= 32'd1;
+        end
+        32'd8: begin
+          state <= 32'd7;
+        end
+        32'd7: begin
+          state <= 32'd6;
+        end
+        32'd6: begin
+          state <= 32'd5;
+        end
+        32'd5: begin
+          state <= 32'd4;
+        end
+        32'd4: begin
+          state <= 32'd3;
+        end
+        32'd3: begin
+          state <= 32'd2;
+        end
+        32'd2: begin
+          state <= 32'd11;
+        end
+        32'd1: begin
+          ;
+        end
         default:;
       endcase
+    end
+  end
+endmodule
+
+module testbench;
+   reg start, reset, clk;
+   wire finish;
+   wire [31:0] return_val;
+   reg [31:0] cycles;
+
+   main m(start, reset, clk, finish, return_val);
+
+   initial begin
+      clk = 0;
+      start = 0;
+      reset = 0;
+      @(posedge clk) reset = 1;
+      @(posedge clk) reset = 0;
+      cycles = 0;
+   end
+
+   always #5 clk = ~clk;
+
+   always @(posedge clk) begin
+      if (finish == 1) begin
+         $display("cycles: %0d", cycles);
+         $display("finished: %0d", return_val);
+         $finish;
+      end
+      cycles <= cycles + 1;
+   end
 endmodule
-- 
cgit