From 1936da65bc9bbfe847c1ff2b7abadff5bdc14f8f Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Tue, 30 Jun 2020 10:20:44 +0100
Subject: Add modifications to Verilog syntax adn implement more notes

---
 main.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'main.tex')

diff --git a/main.tex b/main.tex
index 40151be..7a168ca 100644
--- a/main.tex
+++ b/main.tex
@@ -182,8 +182,8 @@
 \maketitle
 
 \input{introduction}
-\input{verilog}
 \input{algorithm}
+\input{verilog}
 \input{proof}
 \input{evaluation}
 \input{related}
-- 
cgit