From b1723d690ba76c90e810cfbede727a9366e227d1 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 9 Jun 2020 11:34:46 +0100 Subject: Add more citations that I need to include --- main.tex | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'main.tex') diff --git a/main.tex b/main.tex index 4ef0593..a988a1f 100644 --- a/main.tex +++ b/main.tex @@ -204,8 +204,7 @@ Using CompCert, we can therefore build a fully verified high-level synthesis too \end{itemize} } - -\YH{Amazing, thank you, yes it seems like Kundu \textit{et al.} have quite a few papers on formal verification of HLS algorithms using translation validation, as well as~\citet{karfa06_formal_verif_method_sched_high_synth}, all using the SPARK~\cite{gupta03_spark} synthesis tool. And yes thank you, will definitely cite that paper. There seem to be similar early proofs of high-level synthesis like~\citet{hwang91_formal_approac_to_sched_probl}.} +\YH{Amazing, thank you, yes it seems like Kundu \textit{et al.} have quite a few papers on formal verification of HLS algorithms using translation validation, as well as~\citet{karfa06_formal_verif_method_sched_high_synth}, all using the SPARK~\cite{gupta03_spark} synthesis tool. And yes thank you, will definitely cite that paper. There seem to be similar early proofs of high-level synthesis like \citet{hwang91_formal_approac_to_sched_probl} or \citet{grass94_high}. There are also the Occam papers that I need to mention too, like \citet{page91_compil_occam}, \citet{jifeng93_towar}, \citet{perna11_correc_hardw_synth} and \citet{perna12_mechan_wire_wise_verif_handel_c_synth}.} \section{Verilog Semantics} -- cgit