From 4bd624d58d98946f8cef56fbc12b3a7b05b94959 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Tue, 9 Jun 2020 13:52:44 +0100
Subject: Remove unnecessary fields

---
 references.bib | 19 -------------------
 1 file changed, 19 deletions(-)

(limited to 'references.bib')

diff --git a/references.bib b/references.bib
index 8677a96..06e7ac5 100644
--- a/references.bib
+++ b/references.bib
@@ -159,7 +159,6 @@
   author = { {Youngsik Kim} and S. {Kopuri} and N. {Mansouri}},
   title = {Automated formal verification of scheduling process using
                   finite state machines with datapath (FSMD)},
-  tags = {hls, verification},
   booktitle = {International Symposium on Signals, Circuits and
                   Systems. Proceedings, SCS 2003. (Cat. No.03EX720)},
   year = 2004,
@@ -173,7 +172,6 @@
                   Reade, Chris},
   title =        {A Formal Verification Method of Scheduling in High-level
                   Synthesis},
-  tags =         {hls},
   booktitle =    {Proceedings of the 7th International Symposium on Quality
                   Electronic Design},
   year =         2006,
@@ -199,9 +197,6 @@
   url = {https://doi.org/10.1145/1111037.1111042},
   address = {New York, NY, USA},
   isbn = 1595930272,
-  keywords = {the Coq theorem prover, certified compilation, compiler
-                  transformations and optimizations, program proof, semantic
-                  preservation},
   location = {Charleston, South Carolina, USA},
   numpages = 13,
   publisher = {Association for Computing Machinery},
@@ -261,7 +256,6 @@
   author = {C. -. {Hwang} and J. -. {Lee} and Y. -. {Hsu}},
   title = {A Formal Approach To the Scheduling Problem in High Level
                   Synthesis},
-  tags = {hls},
   journal = {IEEE Transactions on Computer-Aided Design of Integrated
                   Circuits and Systems},
   volume = 10,
@@ -270,17 +264,6 @@
   year = 1991,
   doi = {10.1109/43.75629},
   url = {https://doi.org/10.1109/43.75629},
-  keywords = {circuit CAD;integer programming;linear
-                  programming;scheduling;integer LP model;CAD;scheduling
-                  problem;high level synthesis;integer linear
-                  programming;time-constrained scheduling;resource-constrained
-                  scheduling;feasible scheduling;chaining;multicycle
-                  operations;nonpipelined function units;pipelined function
-                  units;functional pipelining;loop folding;mutually exclusive
-                  operations;bus constraint;ASAP;ALAP;list scheduling;High level
-                  synthesis;Digital systems;Space exploration;Scheduling
-                  algorithm;Timing;Integer linear programming;Pipeline
-                  processing;Filters;Hardware design languages;Flow graphs},
   month = {April}
 }
 
@@ -308,7 +291,6 @@
 @inproceedings{jifeng93_towar,
   author = "Jifeng, He and Page, Ian and Bowen, Jonathan",
   title = "Towards a provably correct hardware implementation of occam",
-  tags = {hls},
   booktitle = "Correct Hardware Design and Verification Methods",
   year = 1993,
   pages = "214--225",
@@ -334,7 +316,6 @@
   author = "Perna, Juan and Woodcock, Jim and Sampaio, Augusto and Iyoda,
                   Juliano",
   title = {Correct Hardware Synthesis},
-  tags = {hls},
   journal = "Acta Informatica",
   volume = 48,
   number = 7,
-- 
cgit