From b5fafbdc36a7768002a05278308dc48cfca716e0 Mon Sep 17 00:00:00 2001
From: John Wickerson <j.wickerson@imperial.ac.uk>
Date: Wed, 18 Nov 2020 16:19:20 +0000
Subject: Update on Overleaf.

---
 references.bib | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

(limited to 'references.bib')

diff --git a/references.bib b/references.bib
index bab444d..ec8e945 100644
--- a/references.bib
+++ b/references.bib
@@ -335,6 +335,23 @@
   year = {2008},
 }
 
+@inproceedings{loow19_formalise,
+  author    = {Andreas L{\"{o}}{\"{o}}w and
+               Magnus O. Myreen},
+  title     = {A proof-producing translator for Verilog development in {HOL}},
+  booktitle = {FormaliSE@ICSE},
+  pages     = {99--108},
+  publisher = {{IEEE} / {ACM}},
+  year      = {2019}
+}
+
+@misc{slec_whitepaper,
+  author = {Chauhan, Pankaj},
+  title = {Formally Ensuring Equivalence between C++ and RTL designs},
+  url = {https://bit.ly/2KbT0ki},
+  year = {2020},
+}
+
 @inproceedings{loow19_verif_compil_verif_proces,
   author =       {L\"{o}\"{o}w, Andreas and Kumar, Ramana and Tan, Yong Kiam and
                   Myreen, Magnus O. and Norrish, Michael and Abrahamsson, Oskar
@@ -426,6 +443,14 @@
   year            = 2020,
 }
 
+@misc{intel_hls,
+  author = {Intel},
+  title = {High-level Synthesis Compiler},
+  url = {https://intel.ly/2UDiWr5},
+  urldate = {2020-11-18},
+  year = {2020},
+  }
+
 @misc{intel20_sdk_openc_applic,
   author          = {Intel},
   title           = {{SDK} for {OpenCL} Applications},
@@ -434,6 +459,47 @@
   year            = 2020,
 }
 
+@inproceedings{homsirikamol+14,
+  author    = {Ekawat Homsirikamol and
+               Kris Gaj},
+  title     = {Can high-level synthesis compete against a hand-written code in the
+               cryptographic domain? {A} case study},
+  booktitle = {ReConFig},
+  pages     = {1--8},
+  publisher = {{IEEE}},
+  year      = {2014}
+}
+
+@INPROCEEDINGS{7818341,
+  author={Maxime Pelcat and C\'edric Bourrasset and Luca Maggiani and François Berry},
+  booktitle={2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)}, 
+  title={Design productivity of a high level synthesis compiler versus HDL},
+  year={2016},
+  volume={},
+  number={},
+  pages={140-147},
+  doi={10.1109/SAMOS.2016.7818341}}
+
+@misc{silexicahlshdl,
+author = {Gauthier, Stephane and Wadood, Zubair},
+title = {High-Level Synthesis:
+Can it outperform
+hand-coded HDL?},
+url = {https://bit.ly/2IDhKBR},
+year = {2020},
+}
+
+@inproceedings{bambu_hls,
+  author    = {Christian Pilato and
+               Fabrizio Ferrandi},
+  title     = {Bambu: {A} modular framework for the high level synthesis of memory-intensive
+               applications},
+  booktitle = {{FPL}},
+  pages     = {1--4},
+  publisher = {{IEEE}},
+  year      = {2013}
+}
+
 @inproceedings{nigam20_predic_accel_desig_time_sensit_affin_types,
   author          = {Nigam, Rachit and Atapattu, Sachille and Thomas, Samuel and Li, Zhijing and
                   Bauer, Theodore and Ye, Yuwei and Koti, Apurva and Sampson, Adrian and Zhang,
-- 
cgit