From 06ca7a1b9126e27d6e3c34dbd3637f167be1efc8 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 7 Apr 2021 19:46:27 +0100
Subject: Fix some formatting

---
 verilog.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'verilog.tex')

diff --git a/verilog.tex b/verilog.tex
index 0caf06c..cf5b455 100644
--- a/verilog.tex
+++ b/verilog.tex
@@ -103,7 +103,7 @@ Note that there is no step from \texttt{State} to \texttt{Callstate}; this is be
 Therefore, in addition to the rules shown in Figure~\ref{fig:inferrence_module}, an initial state and final state need to be defined:
 
 \begin{gather*}
-  \inferrule[Initial]{\yhfunction{is\_internal}\ (P.\texttt{main})}{\yhfunction{initial\_state}\ (\yhconstant{Callstate } []\ (P.\texttt{main})\ [])}\\
+  \inferrule[Initial]{\yhfunction{is\_internal}\ (P.\texttt{main})}{\yhfunction{initial\_state}\ (\yhconstant{Callstate } []\ (P.\texttt{main})\ [])}\qquad
   \inferrule[Final]{ }{\yhfunction{final\_state}\ (\yhconstant{Returnstate } []\ n)\ n}
 \end{gather*}
 
-- 
cgit 

