From 0c106400728ab338f08384644a3daeae343d714a Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Mon, 6 Jul 2020 10:14:30 +0100
Subject: Take away some comments

---
 verilog.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'verilog.tex')

diff --git a/verilog.tex b/verilog.tex
index 7b951c7..f11b6a2 100644
--- a/verilog.tex
+++ b/verilog.tex
@@ -93,7 +93,7 @@ We then define the semantics of running the module for one clock cycle in the fo
 
 The \textsc{Module} rule is the main rule for the execution of one clock cycle of the module.  Given that the value of the $s_{t}$ register is the value of the program counter at the current instruction and that the value of the $s_{t}$ register in the resulting association map is equal to the next program counter value, we can then say that if all the module items in the body go from one state to another, that the whole module will step from that state to the other.
 
-\input{verilog_notes}
+%%\input{verilog_notes}
 
 %%% Local Variables:
 %%% mode: latex
-- 
cgit 

