From 3fb145c8ff5d539b8a2891714834420d275dece4 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Fri, 10 Sep 2021 18:43:11 +0100
Subject: Revert the memory model drawing

---
 verilog.tex | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'verilog.tex')

diff --git a/verilog.tex b/verilog.tex
index b0af602..50d7640 100644
--- a/verilog.tex
+++ b/verilog.tex
@@ -130,8 +130,8 @@ The Verilog semantics do not define a memory model for Verilog, as this is not n
 \begin{figure}
   \centering
   \begin{tikzpicture}
-    \fill[compcertmemmodel,rounded corners=3pt] (0,0) rectangle (5,-4.3);
-    \fill[vericertmemmodel,rounded corners=3pt] (7,0) rectangle (12,-4.3);
+    \fill[compcertmemmodel,rounded corners=3pt] (0,0) rectangle (5,-5);
+    \fill[vericertmemmodel,rounded corners=3pt] (7,0) rectangle (12,-5);
     \node[right] at (0,-0.3) {\small \textbf{\compcert{}'s Memory Model}};
     \node[right] at (7,-0.3) {\small \textbf{Verilog Memory Representation}};
     \node[right] (x0) at (0.2,-1.9) {\small 0};
-- 
cgit