From a86ac83c47deda8d0c2f1deabb5c7e75424c22a4 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Fri, 9 Apr 2021 16:17:14 +0100
Subject: Add diagrams

---
 verilog.tex | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

(limited to 'verilog.tex')

diff --git a/verilog.tex b/verilog.tex
index cf5b455..dbcf0e1 100644
--- a/verilog.tex
+++ b/verilog.tex
@@ -109,6 +109,26 @@ Therefore, in addition to the rules shown in Figure~\ref{fig:inferrence_module},
 
 \noindent where the initial state is the \texttt{Callstate} with an empty stack frame and no arguments for the \texttt{main} function of program $P$, where this \texttt{main} function needs to be in the current translation unit.  The final state results in the program output of value $n$ when reaching a \texttt{Returnstate} with an empty stack frame.
 
+\subsection{Memory Model}
+
+\begin{figure}
+  \centering
+  \begin{subfigure}[t]{0.48\linewidth}
+    \includegraphics[width=\linewidth]{diagrams/store_waveform.pdf}
+    \caption{Store waveform.}
+  \end{subfigure}\hfill%
+  \begin{subfigure}[t]{0.48\linewidth}
+    \includegraphics[width=\linewidth]{diagrams/load_waveform.pdf}
+    \caption{Load waveform.}
+  \end{subfigure}
+\end{figure}
+
+\begin{figure}
+  \centering
+  \includegraphics[width=0.5\linewidth]{diagrams/memory_model.pdf}
+  \caption{Change in the memory model during the translation of 3AC to HTL.}
+\end{figure}
+
 %%% Local Variables:
 %%% mode: latex
 %%% TeX-master: "main"
-- 
cgit