module main(reset, clk, finish, return_val);
  reg [31:0] stack [2:0];
  input [0:0] clk, reset;
  output reg [31:0] return_val;
  output reg [0:0] finish;
  reg [31:0] reg_8, reg_4, state, reg_6,
             reg_1, reg_9, reg_5, reg_3, reg_7;
  always @(posedge clk)
    case (state)
      32'd16: reg_9 <= 32'd1;
      32'd15: stack[32'd0] <= reg_9;
      32'd14: reg_8 <= 32'd2;
      32'd13: stack[32'd1] <= reg_8;
      32'd12: reg_7 <= 32'd3;
      32'd11: stack[32'd2] <= reg_7;
      32'd10: reg_3 <= 32'd0;
      32'd9: ;
      32'd8: reg_1 <= 32'd0;
      32'd7: reg_6 <= 32'd0;
      32'd6: reg_5 <= stack[{{{reg_6 + 32'd0}
                           + {reg_1 * 32'd4}} / 32'd4}];
      32'd5: reg_3 <= {reg_3 + {reg_5 + 32'd0}};
      32'd4: reg_1 <= {reg_1 + 32'd1};
      32'd3: ;
      32'd2: reg_4 <= reg_3;
      32'd1: begin finish = 1'd1; return_val = reg_4; end
      default:;
    endcase
  always @(posedge clk)
    if ({reset == 1'd1})
      state <= 32'd16;
    else
      case (state)
        32'd16: state <= 32'd15;
        32'd15: state <= 32'd14;
        32'd14: state <= 32'd13;
        32'd13: state <= 32'd12;
        32'd12: state <= 32'd11;
        32'd11: state <= 32'd10;
        32'd10: state <= 32'd9;
        32'd9: state <= 32'd8;
        32'd8: state <= 32'd7;
        32'd7: state <= 32'd6;
        32'd6: state <= 32'd5;
        32'd5: state <= 32'd4;
        32'd4: state <= 32'd3;
        32'd3: state <= ({$signed(reg_1) < $signed(32'd3)}
                               ? 32'd7 : 32'd2);
        32'd2: state <= 32'd1;
        32'd1: ;
        default:;
      endcase
endmodule