module main(reg_13, reg_14, reg_15, reg_10, reg_11);
  always @(posedge reg_15)
    if ({reg_14 == 32'd1}) begin
      reg_9 <= 32'd15;
    end else begin
      case (reg_9)
        32'd8: begin
          reg_9 <= 32'd7;
        end
        32'd4: begin
          reg_9 <= 32'd3;
        end
        32'd12: begin
          reg_9 <= 32'd11;
        end
        32'd2: begin
          reg_9 <= 32'd1;
        end
        32'd10: begin
          reg_9 <= 32'd9;
        end
        32'd6: begin
          reg_9 <= 32'd5;
        end
        32'd14: begin
          reg_9 <= 32'd13;
        end
        32'd1: begin
          ;
        end
        32'd9: begin
          reg_9 <= 32'd8;
        end
        32'd5: begin
          reg_9 <= 32'd4;
        end
        32'd13: begin
          reg_9 <= 32'd12;
        end
        32'd3: begin
          reg_9 <= ({$signed(reg_1) < $signed(32'd3)} ? 32'd7 : 32'd2);
        end
        32'd11: begin
          reg_9 <= 32'd10;
        end
        32'd7: begin
          reg_9 <= 32'd6;
        end
        32'd15: begin
          reg_9 <= 32'd14;
        end
        default:;
      endcase
    end
  always @(posedge reg_15)
    case (reg_9)
      32'd8: begin
        reg_1 <= 32'd0;
      end
      32'd4: begin
        reg_1 <= {reg_1 + 32'd1};
      end
      32'd12: begin
        reg_12[32'd1] <= reg_7;
      end
      32'd2: begin
        reg_3 <= reg_2;
      end
      32'd10: begin
        reg_12[32'd2] <= reg_6;
      end
      32'd6: begin
        reg_4 <= reg_12[{{{reg_5 + 32'd0} + {reg_1 * 32'd4}} / 32'd4}];
      end
      32'd14: begin
        reg_12[32'd0] <= reg_8;
      end
      32'd1: begin
        reg_10 = 32'd1;
        reg_11 = reg_3;
      end
      32'd9: begin
        reg_2 <= 32'd0;
      end
      32'd5: begin
        reg_2 <= {{reg_2 + reg_4} + 32'd0};
      end
      32'd13: begin
        reg_7 <= 32'd2;
      end
      32'd3: begin
        ;
      end
      32'd11: begin
        reg_6 <= 32'd3;
      end
      32'd7: begin
        reg_5 <= 32'd0;
      end
      32'd15: begin
        reg_8 <= 32'd1;
      end
      default:;
    endcase
  reg [31:0] reg_12 [2:0];
  reg [31:0] reg_8;
  reg [31:0] reg_4;
  reg [31:0] reg_2;
  output reg [0:0] reg_10;
  reg [31:0] reg_6;
  input [0:0] reg_14;
  reg [31:0] reg_1;
  reg [31:0] reg_9;
  reg [31:0] reg_5;
  input [0:0] reg_13;
  reg [31:0] reg_3;
  output reg [31:0] reg_11;
  reg [31:0] reg_7;
  input [0:0] reg_15;
endmodule

module testbench;
   reg start, reset, clk;
   wire finish;
   wire [31:0] return_val;

   main m(start, reset, clk, finish, return_val);

   initial begin
      clk = 0;
      start = 0;
      reset = 0;
      @(posedge clk) reset = 1;
      @(posedge clk) reset = 0;
   end

   always #5 clk = ~clk;

   always @(posedge clk) begin
      if (finish == 1) begin
         $display("finished: %d", return_val);
         $finish;
      end
   end
endmodule