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MEMOCODE '04.}, year = 2004, pages = {69-70}, doi = {10.1109/MEMCOD.2004.1459818}, url = {https://doi.org/10.1109/MEMCOD.2004.1459818}, } @inproceedings{schuiki20_llhd, author = {Schuiki, Fabian and Kurth, Andreas and Grosser, Tobias and Benini, Luca}, title = {LLHD: A Multi-Level Intermediate Representation for Hardware Description Languages}, booktitle = {Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation}, year = 2020, pages = {258-271}, doi = {10.1145/3385412.3386024}, url = {https://doi.org/10.1145/3385412.3386024}, address = {New York, NY, USA}, isbn = 9781450376136, location = {London, UK}, numpages = 14, publisher = {ACM}, series = {PLDI 2020}, } @InProceedings{zhu13_mechan_approac_linkin_operat_seman, author = "Zhu, Huibiao and Liu, Peng and He, Jifeng and Qin, Shengchao", title = "Mechanical Approach to Linking Operational Semantics and Algebraic Semantics for Verilog Using Maude", booktitle = "Unifying Theories of Programming", year = 2013, pages = "164--185", address = "Berlin, Heidelberg", editor = "Wolff, Burkhart and Gaudel, Marie-Claude and Feliachi, Abderrahmane", isbn = "978-3-642-35705-3", publisher = "Springer Berlin Heidelberg", } @inproceedings{poly_hls_zuo2013, title={Improving polyhedral code generation for high-level synthesis}, author={Zuo, Wei and Li, Peng and Chen, Deming and Pouchet, Louis-No{\"e}l and Zhong, Shunan and Cong, Jason}, booktitle={2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS)}, pages={1--10}, year={2013}, organization={IEEE}, doi={https://doi.org/10.1109/CODES-ISSS.2013.6659002} } @INPROCEEDINGS{poly_hls_zhao2017, author={Zhao, Jieru and Feng, Liang and Sinha, Sharad and Zhang, Wei and Liang, Yun and He, Bingsheng}, booktitle={2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}, title={COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications}, year={2017}, volume={}, number={}, pages={430-437}, doi={10.1109/ICCAD.2017.8203809}} @inproceedings{poly_hls_pouchet2013polyhedral, title={Polyhedral-based data reuse optimization for configurable computing}, author={Pouchet, Louis-Noel and Zhang, Peng and Sadayappan, Ponnuswamy and Cong, Jason}, booktitle={Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays}, pages={29--38}, year={2013}, doi={https://doi.org/10.1145/2435264.2435273} } @misc{quartus, author = {Intel}, title = {{Intel® Quartus® Prime Software Suite}}, url = {https://intel.ly/3fpUNhv}, urldate = {2020-07-20}, year = 2020, } @misc{xilinx_vivad_desig_suite, author = {Xilinx}, title = {{Vivado Design Suite}}, url = {https://bit.ly/2wZAmld}, urldate = {2019-01-14}, year = 2019, } @inproceedings{chisel, title={{Chisel: Constructing hardware in a Scala embedded language}}, author={Bachrach, Jonathan and Vo, Huy and Richards, Brian and Lee, Yunsup and Waterman, Andrew and Avi{\v{z}}ienis, Rimas and Wawrzynek, John and Asanovi{\'c}, Krste}, booktitle={DAC Design Automation Conference 2012}, pages={1212--1221}, year={2012}, organization={IEEE}, doi={https://doi.org/10.1145/2228360.2228584}, } @article{aubury1996handel, title={Handel-C language reference guide}, author={Aubury, Matthew and Page, Ian and Randall, Geoff and Saul, Jonathan and Watts, Robin}, journal={Computing Laboratory. Oxford University, UK}, year={1996} } @inproceedings{clarke03_behav_c_veril, author = {E. {Clarke} and D. {Kroening} and K. {Yorav}}, title = {Behavioral consistency of {C} and {Verilog} programs using bounded model checking}, booktitle = {Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)}, year = 2003, pages = {368-371}, doi = {10.1145/775832.775928}, url = {https://doi.org/10.1145/775832.775928}, } @article{besson18_compc, doi = {10.1007/s10817-018-9496-y}, url = {https://doi.org/10.1007/s10817-018-9496-y}, year = {2018}, month = nov, publisher = {Springer Science and Business Media {LLC}}, volume = {63}, number = {2}, pages = {369--392}, author = {Fr{\'{e}}d{\'{e}}ric Besson and Sandrine Blazy and Pierre Wilke}, title = {{CompCertS}: A Memory-Aware Verified C Compiler Using a Pointer as Integer Semantics}, journal = {Journal of Automated Reasoning} } @article{sevcik13_compc, author = {\v{S}ev\v{c}\'{\i}k, Jaroslav and Vafeiadis, Viktor and Zappa Nardelli, Francesco and Jagannathan, Suresh and Sewell, Peter}, title = {CompCertTSO: A Verified Compiler for Relaxed-Memory Concurrency}, year = {2013}, issue_date = {June 2013}, publisher = {ACM}, address = {New York, NY, USA}, volume = {60}, number = {3}, issn = {0004-5411}, url = {https://doi.org/10.1145/2487241.2487248}, doi = {10.1145/2487241.2487248}, abstract = {In this article, we consider the semantic design and verified compilation of a C-like programming language for concurrent shared-memory computation on x86 multiprocessors. The design of such a language is made surprisingly subtle by several factors: the relaxed-memory behavior of the hardware, the effects of compiler optimization on concurrent code, the need to support high-performance concurrent algorithms, and the desire for a reasonably simple programming model. In turn, this complexity makes verified compilation both essential and challenging.We describe ClightTSO, a concurrent extension of CompCert’s Clight in which the TSO-based memory model of x86 multiprocessors is exposed for high-performance code, and CompCertTSO, a formally verified compiler from ClightTSO to x86 assembly language, building on CompCert. CompCertTSO is verified in Coq: for any well-behaved and successfully compiled ClightTSO source program, any permitted observable behavior of the generated assembly code (if it does not run out of memory) is also possible in the source semantics. We also describe some verified fence-elimination optimizations, integrated into CompCertTSO.}, journal = {J. ACM}, month = jun, articleno = {22}, numpages = {50}, keywords = {semantics, Relaxed memory models, verified compilation} } @article{wang20_compc, author = {Wang, Yuting and Xu, Xiangzhe and Wilke, Pierre and Shao, Zhong}, title = {CompCertELF: Verified Separate Compilation of C Programs into ELF Object Files}, year = {2020}, issue_date = {November 2020}, publisher = {ACM}, address = {New York, NY, USA}, volume = {4}, number = {OOPSLA}, url = {https://doi.org/10.1145/3428265}, doi = {10.1145/3428265}, abstract = { We present CompCertELF, the first extension to CompCert that supports verified compilation from C programs all the way to a standard binary file format, i.e., the ELF object format. Previous work on Stack-Aware CompCert provides a verified compilation chain from C programs to assembly programs with a realistic machine memory model. We build CompCertELF by modifying and extending this compilation chain with a verified assembler which further transforms assembly programs into ELF object files. CompCert supports large-scale verification via verified separate compilation: C modules can be written and compiled separately, and then linked together to get a target program that refines the semantics of the program linked from the source modules. However, verified separate compilation in CompCert only works for compilation to assembly programs, not to object files. For the latter, the main difficulty is to bridge the two different views of linking: one for CompCert's programs that allows arbitrary shuffling of global definitions by linking and the other for object files that treats blocks of encoded definitions as indivisible units. We propose a lightweight approach that solves the above problem without any modification to CompCert's framework for verified separate compilation: by introducing a notion of syntactical equivalence between programs and proving the commutativity between syntactical equivalence and the two different kinds of linking, we are able to transit from the more abstract linking operation in CompCert to the more concrete one for ELF object files. By applying this approach to CompCertELF, we obtain the first compiler that supports verified separate compilation of C programs into ELF object files. }, journal = {Proc. ACM Program. Lang.}, month = nov, articleno = {197}, numpages = {28}, keywords = {Generation of Object Files, Assembler Verification, Verified Separate Compilation} } @inproceedings{10.1145/3437992.3439916, author = {L\"{o}\"{o}w, Andreas}, title = {Lutsig: A Verified Verilog Compiler for Verified Circuit Development}, year = {2021}, isbn = {9781450382991}, publisher = {ACM}, address = {New York, NY, USA}, url = {https://doi.org/10.1145/3437992.3439916}, doi = {10.1145/3437992.3439916}, abstract = {We report on a new verified Verilog compiler called Lutsig. Lutsig currently targets (a class of) FPGAs and is capable of producing technology mapped netlists for FPGAs. We have connected Lutsig to existing Verilog development tools, and in this paper we show how Lutsig, as a consequence of this connection, fits into a hardware development methodology for verified circuits in the HOL4 theorem prover. One important step in the methodology is transporting properties proved at the behavioral Verilog level down to technology mapped netlists, and Lutsig is the component in the methodology that enables such transportation.}, booktitle = {Proceedings of the 10th ACM SIGPLAN International Conference on Certified Programs and Proofs}, pages = {46–60}, numpages = {15}, keywords = {hardware verification, hardware synthesis, compiler verification}, location = {Virtual, Denmark}, series = {CPP 2021} } @inproceedings{paulin89_sched_bindin_algor_high_level_synth, author = {Paulin, P. G. and Knight, J. P.}, title = {Scheduling and Binding Algorithms for High-Level Synthesis}, booktitle = {Proceedings of the 26th ACM/IEEE Design Automation Conference}, year = 1989, pages = {1-6}, doi = {10.1145/74382.74383}, url = {https://doi.org/10.1145/74382.74383}, address = {New York, NY, USA}, isbn = 0897913108, location = {Las Vegas, Nevada, USA}, numpages = 6, publisher = {ACM}, series = {DAC '89}, } @inproceedings{venkataramani07_operat, keywords = {operation chaining}, author = {Girish Venkataramani and Goldstein, Seth C.}, booktitle = {2007 IEEE/ACM International Conference on Computer-Aided Design}, title = {Operation chaining asynchronous pipelined circuits}, year = {2007}, volume = {}, number = {}, pages = {442-449}, doi = {10.1109/ICCAD.2007.4397305} } @inproceedings{noronha17_rapid_fpga, keywords = {high-level synthesis, FPGA, inlining, compiler optimisation}, author = {D. H. {Noronha} and J. P. {Pinilla} and S. J. E. {Wilton}}, booktitle = {2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, title = {Rapid circuit-specific inlining tuning for FPGA high-level synthesis}, year = {2017}, volume = {}, number = {}, pages = {1-6}, doi = {10.1109/RECONFIG.2017.8279807} } @software{yann_herklotz_2021_5093839, author = {Yann Herklotz and James D. Pollard and Nadesh Ramanathan and John Wickerson}, title = {ymherklotz/vericert: Vericert v1.2.1}, month = jul, year = 2021, publisher = {Zenodo}, version = {v1.2.1}, doi = {10.5281/zenodo.5093839}, url = {https://doi.org/10.5281/zenodo.5093839} } @INPROCEEDINGS{herklotz21_empir_study_reliab_high_level_synth_tools, author = {Herklotz, Yann and Du, Zewei and Ramanathan, Nadesh and Wickerson, John}, booktitle = {2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, title = {An Empirical Study of the Reliability of High-Level Synthesis Tools}, year = {2021}, volume = {}, number = {}, pages = {219-223}, doi = {10.1109/FCCM51124.2021.00034} }