From 91cc905000ca89a5ccec07271741aad7a848a5d6 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 6 May 2022 16:06:40 +0100 Subject: Remove backslash from type --- chapters/hls.tex | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/chapters/hls.tex b/chapters/hls.tex index ad407b1..b4f75d6 100644 --- a/chapters/hls.tex +++ b/chapters/hls.tex @@ -568,7 +568,7 @@ directly from within the data-path (i.e., inside the always-block on lines 16--3 at several program points, the synthesis tool is unlikely to detect that it can be implemented as a RAM block, and will resort to using lots of registers instead, ruining the circuit's area and performance. To avert this, we arrange that the data-path does not access memory directly, but -simply sets the address it wishes to access and then toggles the \type{u\_en} flag. This activates +simply sets the address it wishes to access and then toggles the \type{u_en} flag. This activates the RAM interface (lines 9--15 of \in{Figure}{a}[fig:accumulator_c_rtl]) on the next falling clock edge, which performs the requested load or store. By factoring all the memory accesses out into a separate interface, we ensure that the underlying array is only accessed from a single program point @@ -593,7 +593,7 @@ take two clock cycles and one clock cycle instead, greatly improving their perfo negative edge of the clock is widely supported by synthesis tools, and does not affect the maximum frequency of the final design. -Secondly, the logic in the enable signal of the RAM (\type{en != u\_en}) is also atypical in +Secondly, the logic in the enable signal of the RAM (\type{en != u_en}) is also atypical in hardware designs. Enable signals are normally manually controlled and inserted into the appropriate states, by using a check like the following in the RAM: \type{en == 1}. This means that the RAM only turns on when the enable signal is set. However, to make the proof simpler and avoid reasoning @@ -606,20 +606,20 @@ complicated, especially in the case where the next state also contains a memory the disable signal should not be added. The method we ultimately chose was to have the RAM become enabled not when the enable signal is high, but when it \emph{toggles} its value. This can be arranged by keeping track of the old value of the enable signal in \type{en} and comparing it to the -current value \type{u\_en} set by the data-path. When the values are different, the RAM gets -enabled, and then \type{en} is set to the value of \type{u\_en}. This ensures that the RAM will +current value \type{u_en} set by the data-path. When the values are different, the RAM gets +enabled, and then \type{en} is set to the value of \type{u_en}. This ensures that the RAM will always be disabled straight after it was used, without having to insert or modify any other states. \startplacemarginfigure[reference={fig:ram_load_store},title={Timing diagrams showing the execution of loads and stores over multiple clock cycles.}] \startfloatcombination[nx=2] - \startplacesubfigure[title={Timing diagram for loads. At time 1, the \type{u\_en} signal is - toggled to enable the RAM. At time 2, \type{d\_out} is set to the value stored at the + \startplacesubfigure[title={Timing diagram for loads. At time 1, the \type{u_en} signal is + toggled to enable the RAM. At time 2, \type{d_out} is set to the value stored at the address in the RAM, which is finally assigned to the register \type{r} at time 3.}] \externalfigure[figures/timing-1.pdf] \stopplacesubfigure - \startplacesubfigure[title={Timing diagram for stores. At time 1, the \type{u\_en} signal is - toggled to enable the RAM, and the address \type{addr} and the data to store \type{d\_in} are + \startplacesubfigure[title={Timing diagram for stores. At time 1, the \type{u_en} signal is + toggled to enable the RAM, and the address \type{addr} and the data to store \type{d_in} are set. On the negative edge at time 2, the data is stored into the RAM.}] \externalfigure[figures/timing-2.pdf] \stopplacesubfigure -- cgit