From 7458e17b2bf5b3c6f342731510f1be589851c3a0 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Tue, 3 May 2022 08:00:29 +0100
Subject: Add pipelining notes

---
 chapters/hls.tex | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'chapters/hls.tex')

diff --git a/chapters/hls.tex b/chapters/hls.tex
index 5e7237a..90dc238 100644
--- a/chapters/hls.tex
+++ b/chapters/hls.tex
@@ -104,8 +104,8 @@ formal semantics.
   \hbox{\starttikzpicture [language/.style={fill=white,rounded corners=3pt,minimum height=7mm},
     continuation/.style={},
     linecount/.style={rounded corners=3pt,dashed}]
-    \fill[compcert,rounded corners=3pt] (-1,-0.5) rectangle (9.9,2);
-    \fill[formalhls,rounded corners=3pt] (-1,-1) rectangle (9.9,-2.4);
+    \fill[compcert,rounded corners=3pt] (-1.2,-0.5) rectangle (10.2,2);
+    \fill[formalhls,rounded corners=3pt] (-1.2,-1) rectangle (10.2,-2.4);
     %\draw[linecount] (-0.95,-0.45) rectangle (3.6,1);
     %\draw[linecount] (4,-0.45) rectangle (7.5,1);
     \node[language] at (-0.3,0) (clight) {Clight};
@@ -124,7 +124,7 @@ formal semantics.
     %%\node[anchor=west] at (-0.9,0.7) {\small $\sim$ 27 kloc};
     %%\node[anchor=west] at (4.1,0.7) {\small $\sim$ 46 kloc};
     %%\node[anchor=west] at (2,-1.5) {\small $\sim$ 17 kloc};
-    \node[align=center] at (3.2,-2) {RAM\blank insertion};
+    \node[align=center] at (3.2,-2) {RAM\\[-0.5ex]insertion};
     \draw[->,thick] (clight) -- (conta);
     \draw[->,thick] (conta) -- (cminor);
     \draw[->,thick] (cminor) -- (rtl);
@@ -186,8 +186,9 @@ Vericert, this event is either a positive (rising) or a negative (falling) clock
 always-blocks triggering on the same event are executed in parallel. Always-blocks can also express
 control-flow using if-statements and case-statements.
 
-\startplacemarginfigure[reference={fig:tutorial:state_machine},title={Hello}]
-  \startfloatcombination [nx=2, ny=1]
+\startplacemarginfigure[reference={fig:tutorial:state_machine},title={Example of a state machine
+    implementation in Verilog and it's corresponding state diagram.}]
+  \startfloatcombination[nx=2, ny=1]
     \startplacesubfigure
       \startframedtext[width={0.9\textwidth},frame=off,offset=none,loffset=3cm,bodyfont=11pt]
       \starthlverilog
@@ -213,7 +214,7 @@ control-flow using if-statements and case-statements.
     \stopplacesubfigure
     \startplacesubfigure
     \hbox{\starttikzpicture
-      \node[draw,circle,inner sep=6pt,fill=red] (s0) at (0,0) {$S_{\mathit{start}} / \mono{x}$};
+      \node[draw,circle,inner sep=6pt] (s0) at (0,0) {$S_{\mathit{start}} / \mono{x}$};
       \node[draw,circle,inner sep=8pt] (s1) at (1.5,-3) {$S_{1} / \mono{1}$};
       \node[draw,circle,inner sep=8pt] (s2) at (3,0) {$S_{0} / \mono{1}$};
       \node (s2s) at ($(s2.west) + (-0.3,1)$) {\mono{00}};
-- 
cgit