From 0fcfc52bb1eb3a4b420ba29c012737fc5fcb69eb Mon Sep 17 00:00:00 2001 From: ymherklotz Date: Thu, 23 Sep 2021 10:05:30 +0000 Subject: deploy: 42e19f2b20c907505a28486a8071147ed6c610fb --- docs/index.html | 2 +- images/hls-flow-handdrawn.svg | 2527 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 2528 insertions(+), 1 deletion(-) create mode 100644 images/hls-flow-handdrawn.svg diff --git a/docs/index.html b/docs/index.html index 2a9f2ce..eda0422 100644 --- a/docs/index.html +++ b/docs/index.html @@ -6,5 +6,5 @@ Docs

Vericert translates C code into a hardware description language called Verilog, which can then be synthesised into hardware, to be placed onto a field-programmable gate array (FPGA) or -application-specific integrated circuit (ASIC).

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

The design shown in Figure 1 shows how Vericert leverages an existing verified C compiler +application-specific integrated circuit (ASIC).

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

The design shown in Figure 1 shows how Vericert leverages an existing verified C compiler called CompCert to perform this translation.

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