From 9a0b1f5ed471e2752480d91f5fc6a433dac714dc Mon Sep 17 00:00:00 2001 From: ymherklotz Date: Sun, 19 Sep 2021 17:08:57 +0000 Subject: deploy: 54b98a4da47ac332827f9f8186256881575b3d76 --- 404.html | 2 +- blog/index.html | 2 +- ...9f57a8e1685690972994e6e1e9ab35c2c25c5d0245ebb00c95ec8272bee21c.css | 1 - ...f27d0aee7c885a97dc865e7209c83dde91bef2046568d3366053c4027e2089.css | 1 + categories/index.html | 2 +- docs/building/index.html | 2 +- docs/coq-style-guide/index.html | 2 +- docs/index.html | 4 ++-- docs/unreleased/index.html | 2 +- docs/using-vericert/index.html | 2 +- future/index.html | 2 +- index.html | 2 +- tags/index.html | 2 +- 13 files changed, 13 insertions(+), 13 deletions(-) delete mode 100644 book.min.5a9f57a8e1685690972994e6e1e9ab35c2c25c5d0245ebb00c95ec8272bee21c.css create mode 100644 book.min.dbf27d0aee7c885a97dc865e7209c83dde91bef2046568d3366053c4027e2089.css diff --git a/404.html b/404.html index 840d0af..90b1469 100644 --- a/404.html +++ b/404.html @@ -1 +1 @@ -404 Page not found | Vericert

404

Page Not Found

Vericert

\ No newline at end of file +404 Page not found | Vericert

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Vericert

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Blog
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.w{color:#888}#book-logo{background-image:url(/vericert-white.svg);height:5rem;background-repeat:no-repeat;background-size:cover}}.book-brand{padding-bottom:1rem}.book-brand p{line-height:1.3;text-align:center}.book-page{background:var(--gray-100);border-radius:20px;padding:3rem}.markdown pre{background-color:var(--body-background)}.markdown h1{font-size:3em}.book-categories-tag{padding-right:1em}.book-tags-tag{padding-right:1em}.markdown .book-by-line{margin-top:0;margin-bottom:.2em}img{margin:1em auto;display:block}figcaption{font-size:.875em} \ No newline at end of file diff --git a/categories/index.html b/categories/index.html index 0a84d66..cd0aa90 100644 --- a/categories/index.html +++ b/categories/index.html @@ -1,4 +1,4 @@ -Categories | Vericert +Categories | Vericert
Categories
\ No newline at end of file diff --git a/docs/building/index.html b/docs/building/index.html index cd26e32..a23c337 100644 --- a/docs/building/index.html +++ b/docs/building/index.html @@ -2,7 +2,7 @@ The project is written in Coq, a theorem prover, which is extracted to OCaml so that it can then be compiled and executed. The dependencies of this project are the following: Coq: theorem prover that is used to also program the HLS tool.">Building Vericert | Vericert + Coq: theorem prover that is used to also program the HLS tool.">Building Vericert | Vericert
Building Vericert

Building Vericert

To build Vericert, the provided Makefile can be used. External dependencies are needed to build the diff --git a/docs/coq-style-guide/index.html b/docs/coq-style-guide/index.html index 429b45c..cbcda1e 100644 --- a/docs/coq-style-guide/index.html +++ b/docs/coq-style-guide/index.html @@ -1,6 +1,6 @@ Coq Style Guide | Vericert +Code organization # Legal banner # Files should begin with a copyright/license banner, as shown in the example above.">Coq Style Guide | Vericert

Coq Style Guide

Coq Style Guide

This style guide was taken from Silveroak, it outlines code style for Coq code in this diff --git a/docs/index.html b/docs/index.html index dd0409f..5e7f5a5 100644 --- a/docs/index.html +++ b/docs/index.html @@ -1,10 +1,10 @@ Docs | Vericert + The design shown in Figure 1 shows how Vericert leverages an existing verified C compiler called CompCert to perform this translation.">Docs | Vericert

Docs

Vericert translates C code into a hardware description language called Verilog, which can then be synthesised into hardware, to be placed onto a field-programmable gate array (FPGA) or -application-specific integrated circuit (ASIC).

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

The design shown in Figure 1 shows how Vericert leverages an existing verified C compiler +application-specific integrated circuit (ASIC).

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

The design shown in Figure 1 shows how Vericert leverages an existing verified C compiler called CompCert to perform this translation.

\ No newline at end of file diff --git a/docs/unreleased/index.html b/docs/unreleased/index.html index 71db939..50abfc8 100644 --- a/docs/unreleased/index.html +++ b/docs/unreleased/index.html @@ -1,6 +1,6 @@ Unreleased Features | Vericert + scheduling, operation chaining, if-conversion, and functions. This page gives some preliminary information on how the features are implemented and how the proofs for the features are being done. Once these features are properly implemented, they will be added to the proper documentation.">Unreleased Features | Vericert
Unreleased Features

Unreleased Features

The following are unreleased features in Vericert that are currently being worked on and have not diff --git a/docs/using-vericert/index.html b/docs/using-vericert/index.html index c752c7f..b42f92b 100644 --- a/docs/using-vericert/index.html +++ b/docs/using-vericert/index.html @@ -1,6 +1,6 @@ Using Vericert | Vericert +void matrix_multiply(int first[2][2], int second[2][2], int multiply[2][2]) { int sum = 0; for (int c = 0; c < 2; c++) { for (int d = 0; d < 2; d++) { for (int k = 0; k < 2; k++) { sum = sum + first[c][k]*second[k][d]; } multiply[c][d] = sum; sum = 0; } } } int main() { int f[2][2] = {{1, 2}, {3, 4}}; int s[2][2] = {{5, 6}, {7, 8}}; int m[2][2] = {{0, 0}, {0, 0}}; matrix_multiply(f, s, m); return m[1][1]; } It can be compiled using the following command, assuming that vericert is somewhere on the path.">Using Vericert | Vericert

Using Vericert

Using Vericert

Vericert can be used to translate a subset of C into Verilog. As a simple example, consider the diff --git a/future/index.html b/future/index.html index f6a0c20..0ade3aa 100644 --- a/future/index.html +++ b/future/index.html @@ -2,7 +2,7 @@ The next interesting optimisations that should be looked at are the following: globals, type support, memory partitioning, and loop pipelining. Globals # Globals are an important feature to add, as have to be handled carefully in HLS, because they have to be placed into memory, and are often used in HLS designs.">Future Work | Vericert + globals, type support, memory partitioning, and loop pipelining. Globals # Globals are an important feature to add, as have to be handled carefully in HLS, because they have to be placed into memory, and are often used in HLS designs.">Future Work | Vericert

Future Work

Future Work

This section contains future work that should be added to Vericert to make it into a better diff --git a/index.html b/index.html index 621794f..f46a016 100644 --- a/index.html +++ b/index.html @@ -1,5 +1,5 @@ Vericert | Vericert +Features # The project is currently a work in progress, so proofs remain to be finished. Currently, the following C features are supported, but are not all proven correct yet:">Vericert | Vericert

Vericert

A formally verified high-level synthesis (HLS) tool written in Coq, building on top of CompCert. diff --git a/tags/index.html b/tags/index.html index 090e745..306bdd2 100644 --- a/tags/index.html +++ b/tags/index.html @@ -1,4 +1,4 @@ -Tags | Vericert +Tags | Vericert

Tags
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