From 45183ec019f667d5333cdda334eebacbdd508bc1 Mon Sep 17 00:00:00 2001 From: ymherklotz Date: Sun, 19 Sep 2021 16:48:27 +0000 Subject: deploy: 79ac5829c25b966214b33e28198eaa279ffe7f15 --- docs/index.html | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'docs/index.html') diff --git a/docs/index.html b/docs/index.html index 419df0b..9a75c28 100644 --- a/docs/index.html +++ b/docs/index.html @@ -1,10 +1,10 @@ Docs | -

+ The design shown in Figure 1 shows how Vericert leverages an existing verified C compiler called CompCert to perform this translation.">Docs | Vericert +

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Vericert translates C code into a hardware description language called Verilog, which can then be +

Vericert translates C code into a hardware description language called Verilog, which can then be synthesised into hardware, to be placed onto a field-programmable gate array (FPGA) or -application-specific integrated circuit (ASIC).

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

The design shown in Figure 1 shows how Vericert leverages an existing verified C compiler +application-specific integrated circuit (ASIC).

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

The design shown in Figure 1 shows how Vericert leverages an existing verified C compiler called CompCert to perform this translation.

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