From 678816865a90216b750b9cf43f570ff3b868350f Mon Sep 17 00:00:00 2001 From: ymherklotz Date: Sat, 16 Jan 2021 22:14:50 +0000 Subject: deploy: baa147fd4935bc7f395847b2377ba1ffcfeb57a1 --- docs/index.html | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 docs/index.html (limited to 'docs/index.html') diff --git a/docs/index.html b/docs/index.html new file mode 100644 index 0000000..c264cdc --- /dev/null +++ b/docs/index.html @@ -0,0 +1,7 @@ +Docs | Vericert +
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Vericert translates C code into a hardware description language called Verilog, which can then be synthesised into hardware, to be placed onto a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC).

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

The design shown in Figure 1 shows how Vericert leverages an existing verified C compiler called CompCert to perform this translation.

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