From 80568aaef48fab6aff08d0cc724909e5afeee5dd Mon Sep 17 00:00:00 2001 From: ymherklotz Date: Sun, 19 Sep 2021 23:17:53 +0000 Subject: deploy: 5508c21e064276aa4d5146b3af5b6f6e9a4c2364 --- docs/index.html | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'docs/index.html') diff --git a/docs/index.html b/docs/index.html index 5e7f5a5..6b5a5be 100644 --- a/docs/index.html +++ b/docs/index.html @@ -2,9 +2,9 @@ Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language. The design shown in Figure 1 shows how Vericert leverages an existing verified C compiler called CompCert to perform this translation.">Docs | Vericert -
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Vericert translates C code into a hardware description language called Verilog, which can then be synthesised into hardware, to be placed onto a field-programmable gate array (FPGA) or -application-specific integrated circuit (ASIC).

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

The design shown in Figure 1 shows how Vericert leverages an existing verified C compiler +application-specific integrated circuit (ASIC).

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

Figure 1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.

The design shown in Figure 1 shows how Vericert leverages an existing verified C compiler called CompCert to perform this translation.

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