Future Work
This section contains future work that should be added to Vericert to make it into a better high-level synthesis tool.
The next interesting optimisations that should be looked at are the following:
Globals #
Globals are an important feature to add, as have to be handled carefully in HLS, because they have to be placed into memory, and are often used in HLS designs. Proper handling of globals would allow for a larger subset of programs to be compiled, even allowing for larger benchmarks to be used, such as CHStone.
Type Support #
It would also be useful to have support for other datatypes in C, such as char or short, as using
these small datatypes is also quite popular in HLS to make the final designs more efficient.
Memory Partitioning #
Memory partitioning is quite an advanced optimisation, which could be combined with the support for globals so as to make memory layouts on the FPGA more efficient and run various memory operations in parallel.
Loop pipelining #
Loop pipelining is an optimisation to schedule loops, instead of only scheduling the instructions inside of the loop. There are two versions of loop pipelining, software and hardware loop pipelining. The former is done purely on instructions, whereas the latter is performed in tandem with scheduling.