From 0c021173b3efb1310370de4b2a6f5444c745022f Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sat, 24 Jul 2021 16:09:09 +0200 Subject: Use main instead of top for synthesising Vericert designs --- scripts/synth.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'scripts') diff --git a/scripts/synth.tcl b/scripts/synth.tcl index 2b032be..e5151e8 100644 --- a/scripts/synth.tcl +++ b/scripts/synth.tcl @@ -77,7 +77,7 @@ proc dump_statistics { } { set outputDir . create_project -in_memory -part xc7z020clg484-1 -force read_verilog main.v -synth_design -mode out_of_context -no_iobuf -top top -part xc7z020clg484-1 +synth_design -mode out_of_context -no_iobuf -top main -part xc7z020clg484-1 write_checkpoint -force $outputDir/post_synth.dcp report_timing_summary -file $outputDir/post_synth_timing_summary.rpt report_utilization -file $outputDir/post_synth_util.rpt -- cgit