From 6cff3d1683ed19ca497975394d9a11df1b027c28 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 13 Jan 2021 17:57:23 +0000
Subject: Add missing modules to extraction and compile

---
 src/Compiler.v | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'src/Compiler.v')

diff --git a/src/Compiler.v b/src/Compiler.v
index 5895e1d..ce36d5b 100644
--- a/src/Compiler.v
+++ b/src/Compiler.v
@@ -74,7 +74,8 @@ From vericert Require
      HTLgen
      RTLBlock
      RTLBlockgen
-     HTLSchedulegen
+     RTLPargen
+     HTLPargen
      Pipeline.
 
 From compcert Require Import Smallstep.
@@ -245,7 +246,8 @@ Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program :=
    @@ print (print_RTL 8)
   @@@ RTLBlockgen.transl_program
    @@ print print_RTLBlock
-  @@@ HTLSchedulegen.transl_program
+  @@@ RTLPargen.transl_program
+  @@@ HTLPargen.transl_program
    @@ print print_HTL
    @@ Veriloggen.transl_program.
 
-- 
cgit