From ae30c51b001b43e292c1e2b48799bf197d7b89ec Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 17 Apr 2020 14:55:57 +0100 Subject: Extract simulator --- src/Compiler.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/Compiler.v') diff --git a/src/Compiler.v b/src/Compiler.v index 5b4ef0a..697732d 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -1,4 +1,4 @@ -(* +(* -*- mode: coq -*- * CoqUp: Verified high-level synthesis. * Copyright (C) 2019-2020 Yann Herklotz * @@ -74,7 +74,7 @@ Proof. intros. destruct x; simpl. rewrite print_identity. auto. auto. Qed. -Definition transf_backend (r : RTL.program) : res Verilog.module := +Definition transf_backend (r : RTL.program) : res Verilog.module := OK r @@@ Veriloggen.transf_program. -- cgit