From cf9323858362f2c7d4f1ecd99c7bf93d30cf5ea3 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 2 Feb 2021 12:55:37 +0000 Subject: Add Vrange and predicates --- src/Compiler.v | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/Compiler.v') diff --git a/src/Compiler.v b/src/Compiler.v index 0578f57..2406dad 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -232,8 +232,6 @@ Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program := @@ print (print_RTL 6) @@@ time "Unused globals" Unusedglob.transform_program @@ print (print_RTL 7) - @@ Pipeline.transf_program - @@ print (print_RTL 8) @@@ RTLBlockgen.transl_program @@ print print_RTLBlock @@@ RTLPargen.transl_program -- cgit