From 6e290b7049fc874c32e62ab816493dc5200ebc4e Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 18 Feb 2020 12:08:15 +0000 Subject: Update Verilog AST with flat array --- src/Verilog/VerilogAST.v | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/Verilog') diff --git a/src/Verilog/VerilogAST.v b/src/Verilog/VerilogAST.v index 362fe45..5886652 100644 --- a/src/Verilog/VerilogAST.v +++ b/src/Verilog/VerilogAST.v @@ -32,6 +32,9 @@ Inductive value : Type := | VBool (b : bool) | VArray (l : list value). +Inductive literal : Type := +| LitArray (l : list bool). + Definition cons_value (a b : value) : value := match a, b with | VBool _, VArray b' => VArray (a :: b') -- cgit