From 40df7e29e263a5dad8fb894f2d39753d750ac8e3 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 31 Mar 2020 19:40:42 +0100 Subject: Convert from RTL to Verilog directly --- src/extraction/Extraction.v | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/extraction') diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index e71721e..4403019 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -126,12 +126,15 @@ Extract Constant Compopts.debug => (* Compiler *) Extract Constant Compiler.print_Clight => "PrintClight.print_if". Extract Constant Compiler.print_Cminor => "PrintCminor.print_if". +Extract Constant driver.Compiler.print_RTL => "PrintRTL.print_if". Extract Constant Compiler.print_RTL => "PrintRTL.print_if". Extract Constant Compiler.print_LTL => "PrintLTL.print_if". Extract Constant Compiler.print_Mach => "PrintMach.print_if". Extract Constant Compiler.print => "fun (f: 'a -> unit) (x: 'a) -> f x; x". Extract Constant Compiler.time => "Timing.time_coq". +Extract Constant Coquplib.debug_print => "print_newline". + (*Extraction Inline Compiler.apply_total Compiler.apply_partial.*) (* Cabs *) -- cgit