From 05347ca5126f335b0479b71a4576b141e082fab5 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Tue, 2 Mar 2021 10:27:33 +0000
Subject: Add RAM to HTL

---
 src/hls/HTL.v | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/hls/HTL.v')

diff --git a/src/hls/HTL.v b/src/hls/HTL.v
index c8a0041..1949785 100644
--- a/src/hls/HTL.v
+++ b/src/hls/HTL.v
@@ -67,6 +67,7 @@ Record module: Type :=
     mod_clk : reg;
     mod_scldecls : AssocMap.t (option Verilog.io * Verilog.scl_decl);
     mod_arrdecls : AssocMap.t (option Verilog.io * Verilog.arr_decl);
+    mod_ram : option (reg * reg * reg * reg);
     mod_wf : (map_well_formed mod_controllogic /\ map_well_formed mod_datapath);
   }.
 
-- 
cgit