From cf9949a5151aa9ed86554fb31c2a56fad0614a10 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Thu, 25 Jun 2020 18:04:49 +0100
Subject: Progress on proof of Veriloggen

---
 src/verilog/HTL.v | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'src/verilog/HTL.v')

diff --git a/src/verilog/HTL.v b/src/verilog/HTL.v
index 0bf5072..a3623f0 100644
--- a/src/verilog/HTL.v
+++ b/src/verilog/HTL.v
@@ -99,12 +99,14 @@ Inductive state : Type :=
 
 Inductive step : genv -> state -> Events.trace -> state -> Prop :=
 | step_module :
-    forall g m st sf ctrl data
+    forall g m st sf ctrl data ist
       asr asa
       basr1 basa1 nasr1 nasa1
       basr2 basa2 nasr2 nasa2
       asr' asa'
       f stval pstval,
+      asr!(m.(mod_st)) = Some ist ->
+      valueToPos ist = st ->
       m.(mod_controllogic)!st = Some ctrl ->
       m.(mod_datapath)!st = Some data ->
       Verilog.stmnt_runp f
-- 
cgit