From 7ad63f341fe3c28ef20bfde755bdf21403077504 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 12 Jun 2020 11:38:14 +0100 Subject: Remove Verilog proofs --- src/verilog/HTL.v | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/verilog/HTL.v') diff --git a/src/verilog/HTL.v b/src/verilog/HTL.v index 2e4ef1a..c07d672 100644 --- a/src/verilog/HTL.v +++ b/src/verilog/HTL.v @@ -47,7 +47,12 @@ Record module: Type := mod_st : reg; mod_stk : reg; mod_finish : reg; - mod_return : reg + mod_return : reg; + mod_start : reg; + mod_reset : reg; + mod_clk : reg; + mod_scldecls : AssocMap.t (option Verilog.io * Verilog.scl_decl); + mod_arrdecls : AssocMap.t (option Verilog.io * Verilog.arr_decl); }. Definition fundef := AST.fundef module. -- cgit