From 5cf10a4c70763cbb95747b19ac35b57a9dee4dd5 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Fri, 24 Jul 2020 10:22:13 +0100
Subject: More renames to get it to compile

---
 src/verilog/PrintVerilog.ml | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'src/verilog/PrintVerilog.ml')

diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml
index f348ee6..0f64066 100644
--- a/src/verilog/PrintVerilog.ml
+++ b/src/verilog/PrintVerilog.ml
@@ -17,7 +17,7 @@
  *)
 
 open Verilog
-open Value
+open ValueInt
 open Datatypes
 
 open Camlcoq
@@ -70,7 +70,9 @@ let unop = function
 
 let register a = sprintf "reg_%d" (P.to_int a)
 
-let literal l = sprintf "%d'd%d" (Nat.to_int l.vsize) (Z.to_int (uvalueToZ l))
+(*let literal l = sprintf "%d'd%d" (Nat.to_int l.vsize) (Z.to_int (uvalueToZ l))*)
+
+let literal l = sprintf "32'd%ld" (camlint_of_coqint l)
 
 let rec pprint_expr = function
   | Vlit l -> literal l
-- 
cgit