From a23cc48f449ffbfd347f833965c1e04b88e0009a Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sun, 14 Jun 2020 14:12:38 +0100 Subject: Add more unproven instructions, Admitted equiv to spec --- src/verilog/PrintVerilog.ml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/verilog/PrintVerilog.ml') diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml index 700b8e3..a0f3ab3 100644 --- a/src/verilog/PrintVerilog.ml +++ b/src/verilog/PrintVerilog.ml @@ -58,7 +58,8 @@ let pprint_binop l r = | Vor -> unsigned "|" | Vxor -> unsigned "^" | Vshl -> unsigned "<<" - | Vshr -> unsigned ">>" + | Vshr -> signed ">>>" + | Vshru -> unsigned ">>" let unop = function | Vneg -> " ~ " -- cgit