From 8eab4b3fb7fccf3b93711b0ef7c9779926bcf252 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 17 Apr 2020 14:56:46 +0100 Subject: Fix printing with new Verilog AST --- src/verilog/PrintVerilog.mli | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/verilog/PrintVerilog.mli') diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli index 181a9d2..b4d2937 100644 --- a/src/verilog/PrintVerilog.mli +++ b/src/verilog/PrintVerilog.mli @@ -17,3 +17,5 @@ *) val print_program : out_channel -> Verilog.coq_module -> unit + +val print_result : (BinNums.positive * Value.value) list -> unit -- cgit