From 0695114f5f1b758177d2e43989be5432710db6a5 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 31 Mar 2020 10:45:13 +0100 Subject: Improve Verilog error messages --- src/verilog/Verilog.v | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/verilog/Verilog.v') diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v index 225d35d..09eb914 100644 --- a/src/verilog/Verilog.v +++ b/src/verilog/Verilog.v @@ -43,7 +43,10 @@ Definition posToValue (p : positive) : value := mkvalue size (Word.posToWord size p). Definition intToValue (i : Integers.int) : value := - mkvalue 32%nat (Word.natToWord 32%nat (Z.to_nat (Integers.Int.unsigned i))). + mkvalue 32%nat (Word.ZToWord 32%nat (Integers.Int.unsigned i)). + +Definition valueToZ (v : value) : Z := + Word.uwordToZ v.(vword). Definition state : Type := PositiveMap.t value * PositiveMap.t value. -- cgit