From fcb129725a68a052a079f882396be8e28142e1e0 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 7 Jul 2020 13:50:55 +0100 Subject: Only translate_cond left --- src/verilog/Verilog.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/verilog/Verilog.v') diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v index 78b057d..43df3dd 100644 --- a/src/verilog/Verilog.v +++ b/src/verilog/Verilog.v @@ -143,7 +143,8 @@ Inductive binop : Type := | Vxor : binop (** xor (binary [^|]) *) | Vshl : binop (** shift left ([<<]) *) | Vshr : binop (** shift right ([>>>]) *) -| Vshru : binop. (** shift right unsigned ([>>]) *) +| Vshru : binop (** shift right unsigned ([>>]) *) +| Vror : binop. (** shift right unsigned ([>>]) *) (** ** Unary Operators *) @@ -324,6 +325,7 @@ Definition binop_run (op : binop) (v1 v2 : value) : option value := | Vshl => Some (Int.shl v1 v2) | Vshr => Some (Int.shr v1 v2) | Vshru => Some (Int.shru v1 v2) + | Vror => Some (Int.ror v1 v2) end. Definition unop_run (op : unop) (v1 : value) : value := -- cgit