From 65ac86da554770ba0e3a24d187037c6a72a8725b Mon Sep 17 00:00:00 2001 From: Nadesh Ramanathan Date: Tue, 7 Jul 2020 15:33:25 +0100 Subject: added counter in testbench --- src/verilog/PrintVerilog.ml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/verilog') diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml index 5265c97..f8d597a 100644 --- a/src/verilog/PrintVerilog.ml +++ b/src/verilog/PrintVerilog.ml @@ -169,9 +169,12 @@ let testbench = "module testbench; always #5 clk = ~clk; + reg [31:0] count; + initial count = 0; always @(posedge clk) begin + count <= count + 1; if (finish == 1) begin - $display(\"finished: %d\", return_val); + $display(\"finished: %d cycles %d\", return_val, count); $finish; end end -- cgit