From f8ff27915f8c4d5fb6f31ec2a0a73f65cf604c43 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 30 Jun 2020 19:52:59 +0100 Subject: Add htl pretty printing --- src/verilog/PrintVerilog.ml | 2 +- src/verilog/PrintVerilog.mli | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'src/verilog') diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml index 6d10887..5265c97 100644 --- a/src/verilog/PrintVerilog.ml +++ b/src/verilog/PrintVerilog.ml @@ -78,7 +78,7 @@ let rec pprint_expr = function | Vvari (s, i) -> concat [register s; "["; pprint_expr i; "]"] | Vinputvar s -> register s | Vunop (u, e) -> concat ["("; unop u; pprint_expr e; ")"] - | Vbinop (op, a, b) -> concat ["("; pprint_binop (pprint_expr a) (pprint_expr b) op; ")"] + | Vbinop (op, a, b) -> concat [pprint_binop (pprint_expr a) (pprint_expr b) op] | Vternary (c, t, f) -> concat ["("; pprint_expr c; " ? "; pprint_expr t; " : "; pprint_expr f; ")"] let rec pprint_stmnt i = diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli index 6544e52..62bf63f 100644 --- a/src/verilog/PrintVerilog.mli +++ b/src/verilog/PrintVerilog.mli @@ -16,6 +16,8 @@ * along with this program. If not, see . *) +val pprint_stmnt : int -> Verilog.stmnt -> string + val print_value : out_channel -> Value.value -> unit val print_program : bool -> out_channel -> Verilog.program -> unit -- cgit