From 5ff4baa248397b89b5b66838cd57419191537d3f Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Thu, 1 Apr 2021 01:36:52 +0100
Subject: Add 0 initialisation

---
 src/hls/PrintVerilog.ml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml
index f618d54..a55193d 100644
--- a/src/hls/PrintVerilog.ml
+++ b/src/hls/PrintVerilog.ml
@@ -142,7 +142,7 @@ let pprint_edge_top i = function
 let declare t =
   function (r, sz) ->
     concat [ t; " ["; sprintf "%d" (Nat.to_int sz - 1); ":0] ";
-             register r; ";\n" ]
+             register r; " = 0;\n" ]
 
 let declarearr t =
   function (r, sz, ln) ->
-- 
cgit