From d023058aceaa5309ee00e99744fe0c9f5df15ced Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Thu, 12 Aug 2021 02:03:14 +0200
Subject: Fix pretty printing issue in Verilog

---
 src/hls/PrintVerilog.ml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml
index a2700a1..a5fa554 100644
--- a/src/hls/PrintVerilog.ml
+++ b/src/hls/PrintVerilog.ml
@@ -75,7 +75,7 @@ let pprint_binop l r =
 
 let unop = function
   | Vneg -> " - "
-  | Vnot -> " ! "
+  | Vnot -> " ~ "
 
 let register a =
   match PMap.find_opt a !name_map with
-- 
cgit