From 2f424a8b7b1acd7bbf81c68f64ba2e26bb46b315 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Mon, 15 Nov 2021 21:01:36 +0000 Subject: Use new RAM defined in FunctionalUnits.v --- src/hls/Memorygen.v | 5 +++-- src/hls/Veriloggen.v | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/hls/Memorygen.v b/src/hls/Memorygen.v index 96c11c3..4ff4a19 100644 --- a/src/hls/Memorygen.v +++ b/src/hls/Memorygen.v @@ -35,6 +35,7 @@ Require Import vericert.hls.Verilog. Require Import vericert.hls.HTL. Require Import vericert.hls.AssocMap. Require Import vericert.hls.Array. +Require Import vericert.hls.FunctionalUnits. Local Open Scope positive. Local Open Scope assocmap. @@ -459,8 +460,8 @@ Lemma forall_ram_lt : forall_ram (fun x => x < max_reg_module m + 1) r. Proof. assert (X: forall a b c, a < b + 1 -> a < Pos.max c b + 1) by lia. - unfold forall_ram; simplify; unfold max_reg_module; repeat apply X; - unfold max_reg_ram; rewrite H; try lia. + unfold forall_ram; simplify; unfold HTL.max_reg_module; repeat apply X; + unfold HTL.max_reg_ram; rewrite H; try lia. Qed. #[local] Hint Resolve forall_ram_lt : mgen. diff --git a/src/hls/Veriloggen.v b/src/hls/Veriloggen.v index aba2293..035e7a4 100644 --- a/src/hls/Veriloggen.v +++ b/src/hls/Veriloggen.v @@ -25,6 +25,7 @@ Require Import vericert.hls.AssocMap. Require Import vericert.hls.HTL. Require Import vericert.hls.ValueInt. Require Import vericert.hls.Verilog. +Require Import vericert.hls.FunctionalUnits. Definition transl_list_fun (a : node * Verilog.stmnt) := let (n, stmnt) := a in -- cgit