From 46d76082ae7039832f597f73720f701a866261a4 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 22 Apr 2020 00:11:40 +0100
Subject: Improve printing of results

---
 src/verilog/PrintVerilog.ml  | 16 ++++++++++------
 src/verilog/PrintVerilog.mli |  4 +++-
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml
index 17c0b16..29c4f5a 100644
--- a/src/verilog/PrintVerilog.ml
+++ b/src/verilog/PrintVerilog.ml
@@ -174,9 +174,13 @@ let pprint_module i n m =
 
 let print_program pp v = pstr pp (pprint_module 0 "main" v)
 
-let rec print_result =
-  function
-  | [] -> ()
-  | (r, v) :: ls ->
-    printf "%s -> %s\n" (register r) (literal v);
-    print_result ls
+let print_result pp lst =
+  let rec print_result_in pp = function
+    | [] -> fprintf pp "]\n"
+    | (r, v) :: ls ->
+      fprintf pp "%s -> %s; " (register r) (literal v);
+      print_result_in pp ls in
+  fprintf pp "[ ";
+  print_result_in pp lst
+
+let print_value pp v = fprintf pp "%s" (literal v)
diff --git a/src/verilog/PrintVerilog.mli b/src/verilog/PrintVerilog.mli
index b4d2937..c9fca8e 100644
--- a/src/verilog/PrintVerilog.mli
+++ b/src/verilog/PrintVerilog.mli
@@ -16,6 +16,8 @@
  * along with this program.  If not, see <https://www.gnu.org/licenses/>.
  *)
 
+val print_value : out_channel -> Value.value -> unit
+
 val print_program : out_channel -> Verilog.coq_module -> unit
 
-val print_result : (BinNums.positive * Value.value) list -> unit
+val print_result : out_channel -> (BinNums.positive * Value.value) list -> unit
-- 
cgit