From a8aef8ab043500f10cfb82ee5d86efedba50cae4 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Tue, 31 May 2022 02:07:01 +0100
Subject: Use the .sv extension for Verilog

---
 test/Makefile | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/test/Makefile b/test/Makefile
index aa76e70..58a3c12 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -17,10 +17,10 @@ all: $(TESTS)
 %.gcc: %.o
 	@$(CC) $(CFLAGS) -o $@ $<
 
-%.v: %.c
+%.sv: %.c
 	$(VERICERT) $(VERICERT_OPTS) -o $@ $<
 
-%.iver: %.v
+%.iver: %.sv
 	@$(IVERILOG) $(IVERILOG_OPTS) -o $@ -- $<
 
 %.veri.out: %.iver
@@ -31,4 +31,4 @@ all: $(TESTS)
 	@printf "\033[0;36mOK\033[0m\t$(patsubst %.check,%,$@)\n"
 
 clean:
-	rm -f *.check *.gcc *.gcc.out *.o *.v *.iver *.veri.out
+	rm -f *.check *.gcc *.gcc.out *.o *.sv *.iver *.veri.out
-- 
cgit