From b32e7574864cde80f8f5283431c21a6803a89108 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Thu, 10 Aug 2023 11:17:19 +0100
Subject: Fix backend hardware generation and scheduling

---
 scripts/synth.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'scripts/synth.tcl')

diff --git a/scripts/synth.tcl b/scripts/synth.tcl
index a2fb722..f5a2388 100644
--- a/scripts/synth.tcl
+++ b/scripts/synth.tcl
@@ -76,7 +76,7 @@ proc dump_statistics {  } {
 }; #END PROC
 set outputDir .
 create_project -in_memory -part xc7z020clg484-1 -force
-read_verilog -sv main.v
+read_verilog -sv main.sv
 synth_design -mode out_of_context -no_iobuf -top main -part xc7z020clg484-1
 write_checkpoint -force $outputDir/post_synth.dcp
 report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
-- 
cgit