From 1b0d7b8da1ab71af0577c516b2618aeb94abbc34 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sun, 14 Nov 2021 22:23:43 +0000 Subject: Add RTLParFU to top-level --- src/Compiler.v | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/Compiler.v') diff --git a/src/Compiler.v b/src/Compiler.v index ecea2fc..056e404 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -65,6 +65,7 @@ Require vericert.hls.HTLgen. Require vericert.hls.RTLBlock. Require vericert.hls.RTLBlockgen. Require vericert.hls.RTLPargen. +Require vericert.hls.RTLParFUgen. Require vericert.hls.HTLPargen. Require vericert.hls.Pipeline. Require vericert.hls.IfConversion. @@ -246,6 +247,7 @@ Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program := @@ print (print_RTLBlock 1) @@@ RTLPargen.transl_program @@ print (print_RTLPar 0) + @@@ RTLParFUgen.transl_program @@@ HTLPargen.transl_program @@ print (print_HTL 0) @@ Veriloggen.transl_program. -- cgit