From 8a0bd7b74939b65a89b81352b238d1d8252fb278 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Thu, 17 Dec 2020 10:04:21 +0000
Subject: Add extraction and loop pipelining stage

---
 src/Compiler.v | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src/Compiler.v')

diff --git a/src/Compiler.v b/src/Compiler.v
index 7df00d8..5895e1d 100644
--- a/src/Compiler.v
+++ b/src/Compiler.v
@@ -74,7 +74,8 @@ From vericert Require
      HTLgen
      RTLBlock
      RTLBlockgen
-     HTLSchedulegen.
+     HTLSchedulegen
+     Pipeline.
 
 From compcert Require Import Smallstep.
 
@@ -240,6 +241,8 @@ Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program :=
    @@ print (print_RTL 6)
   @@@ time "Unused globals" Unusedglob.transform_program
    @@ print (print_RTL 7)
+   @@ Pipeline.transf_program
+   @@ print (print_RTL 8)
   @@@ RTLBlockgen.transl_program
    @@ print print_RTLBlock
   @@@ HTLSchedulegen.transl_program
-- 
cgit