From 997b768ac8fa7f5f741671d9e4c00b9ea8f0680c Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 16 Feb 2021 19:57:08 +0000 Subject: Add option to turn off if-conversion --- src/Compiler.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/Compiler.v') diff --git a/src/Compiler.v b/src/Compiler.v index 27cb80c..d99ce56 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -68,6 +68,7 @@ Require vericert.hls.RTLPargen. Require vericert.hls.HTLPargen. Require vericert.hls.Pipeline. Require vericert.hls.IfConversion. +Require vericert.HLSOpts. Require Import vericert.hls.HTLgenproof. @@ -235,7 +236,7 @@ Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program := @@ print (print_RTL 7) @@@ RTLBlockgen.transl_program @@ print (print_RTLBlock 1) - @@ IfConversion.transf_program + @@ total_if HLSOpts.optim_if_conversion IfConversion.transf_program @@ print (print_RTLBlock 2) @@@ RTLPargen.transl_program @@@ HTLPargen.transl_program -- cgit