From 1ceb1a28f0e08406862f03863c5d00639ada147d Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 12 Jun 2020 11:37:00 +0100 Subject: Fix top level invocation to translate through HTL --- src/Simulator.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/Simulator.v') diff --git a/src/Simulator.v b/src/Simulator.v index 930971b..83d3e96 100644 --- a/src/Simulator.v +++ b/src/Simulator.v @@ -16,7 +16,7 @@ * along with this program. If not, see . *) -From Coq Require Import FSets.FMapPositive. +(*From Coq Require Import FSets.FMapPositive. From compcert Require Import Errors. @@ -33,3 +33,4 @@ Definition simulate (n : nat) (m : Verilog.module) : res (Value.value * list (po end. Local Close Scope error_monad_scope. +*) -- cgit