From b8107dbffc3c9a27b7beb4014883a55102389a29 Mon Sep 17 00:00:00 2001 From: Michalis Pardalos Date: Sat, 1 May 2021 21:06:44 +0100 Subject: Handle declarations of externctrl regs in Verilog --- src/common/Maps.v | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/common') diff --git a/src/common/Maps.v b/src/common/Maps.v index 2db5114..21a1d9e 100644 --- a/src/common/Maps.v +++ b/src/common/Maps.v @@ -88,4 +88,11 @@ Proof. - reflexivity. Qed. +Definition contains (A: Type) (i: positive) (m: t A) : bool := + match get i m with + | Some _ => true + | None => false + end. + + End PTree. -- cgit